matthew/sonic-buildimage
Archived
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[YANG]: Update port Yang models to support multi-asic platform (#10113)

Browse Source 
Why I did it
Multi-asic platform add aisc_port_name and role to PORT table, and port_index range is changed.

How I did it
Update sonic-port.yang, add asic_port_name and role, and remove range limitation.

How to verify it
Run UT for sonic-yang-models.

Signed-off-by: Gang Lv ganglv@microsoft.com
This commit is contained in:
ganglv 2022-03-07 15:54:05 +08:00 committed by GitHub
parent eec49a2e09
commit 78e867a794
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 96 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/sonic-yang-models/tests/files/sample_config_db.json
View File

@ -420,7 +420,10 @@
"description": "",
"speed": "11100",
"tpid": "0x8100",
"admin_status": "up"
"admin_status": "up",
"index": "0",
"asic_port_name": "Eth0-ASIC1",
"role": "Ext"
},
"Ethernet1": {
"alias": "Eth1/2",

8
src/sonic-yang-models/tests/yang_model_tests/tests/port.json
View File

@ -73,5 +73,13 @@
"PORT_INVALID_MUX_CABLE_TEST": {
"desc": "PORT_INVALID_MUX_CABLE_TEST non-boolean values, expect fail",
"eStrKey": "InvalidValue"
},
"PORT_VALID_MULTIASIC_TEST": {
"desc": "PORT_VALID_MULTIASIC_TEST no failure."
},
"PORT_INVALID_MULTIASIC_TEST": {
"desc": "PORT_INVALID_MULTIASIC_TEST invalid role pattern, expect fail",
"eStrKey": "Pattern"
}
}

71
src/sonic-yang-models/tests/yang_model_tests/tests_config/port.json
View File

@ -314,5 +314,76 @@
]
}
}
},
"PORT_VALID_MULTIASIC_TEST": {
"sonic-port:sonic-port": {
"sonic-port:PORT": {
"PORT_LIST": [
{
"name": "Ethernet8",
"alias": "eth8",
"lanes": "65",
"speed": 50000,
"index": "0",
"asic_port_name": "Eth8-ASIC1",
"role": "Ext"
},
{
"name": "Ethernet9",
"alias": "eth9",
"lanes": "66",
"speed": 50000,
"index": "1",
"asic_port_name": "Eth9-ASIC1"
},
{
"name": "Ethernet10",
"alias": "eth10",
"lanes": "67",
"speed": 50000,
"index": "2",
"asic_port_name": "Eth10-ASIC1",
"role": "Int"
},
{
"name": "Ethernet11",
"alias": "eth11",
"lanes": "68",
"speed": 50000,
"index": "3",
"asic_port_name": "Eth11-ASIC1",
"role": "Inb"
},
{
"name": "Ethernet12",
"alias": "eth12",
"lanes": "69",
"speed": 50000,
"index": "4",
"asic_port_name": "Eth12-ASIC1",
"role": "Rec"
}
]
}
}
},
"PORT_INVALID_MULTIASIC_TEST": {
"sonic-port:sonic-port": {
"sonic-port:PORT": {
"PORT_LIST": [
{
"name": "Ethernet8",
"alias": "eth8",
"lanes": "65",
"speed": 50000,
"index": "0",
"asic_port_name": "Eth8-ASIC1",
"role": "Invalid"
}
]
}
}
}
}

15
src/sonic-yang-models/yang-models/sonic-port.yang
View File

@ -110,9 +110,20 @@ module sonic-port{
}
leaf index {
type uint16 {
range 0..256;
type uint16;
}
leaf asic_port_name {
type string;
description "port name in asic and asic name, e.g Eth0-ASIC1";
}
leaf role {
type string {
pattern "Ext|Int|Inb|Rec";
}
description "Internal port or External port for multi-asic platform";
default "Ext";
}
leaf admin_status {