[7050] updating 7050 MMU configurations (#7801)

Why I did it
7050 S4Q31 mmu configuration is missing ALPM configurations, causing not enough memory reserved for routes. Orchagent crashes on a nightly testbed with 6400 route entries.

How I did it
Add the missing ALPM configurations.

How to verify it
Load the configuration on testbed and verified new configuration exists and no more crash.

Signed-off-by: Ying Xie ying.xie@microsoft.com

device/arista/x86_64-arista_7050_qx32s/Arista-7050QX-32S-S4Q31/td2-a7050-q31s4-31x40G-4x10G.config.bcm

@@ -1,17 +1,51 @@
+# ALPM enable
+l3_alpm_enable=2
+ipv6_lpm_128b_enable=1
+l2_mem_entries=32768
+l3_mem_entries=16384
+
+# From old config file
+os=unix
+higig2_hdr_mode=1
+
+# Parity
+parity_correction=1
+parity_enable=1
+stat_if_parity_enable=0
+
+# l2 thread related config vars
+l2xmsg_hostbuf_size=8192
+l2xmsg_mode=1
+
+bcm_num_cos=8
+bcm_stat_interval=2000000
+lls_num_l2uc=12
+max_vp_lags=0
+miim_intr_enable=0
+mmu_lossless=0
+module_64ports=0
+
+stable_size=0x2000000
+
+tdma_timeout_usec=5000000
+tslam_timeout_usec=15000000
+cdma_timeout_usec=15000000
+dma_desc_timeout_usec=15000000
+
+###############################
+serdes_fiber_pref=1
+###############################
+mdio_output_delay=0x0d
+###############################
+xgxs_lcpll_xtal_refclk=1
+tdma_intr_enable=1
+tslam_intr_enable=1
+table_dma_enable=1
+
 arl_clean_timeout_usec=15000000
-bcm_num_cos.0=8
 bcm_stat_flags=1
 bcm_stat_jumbo.0=9236
-cdma_timeout_usec.0=15000000
+
-dma_desc_timeout_usec.0=15000000
-higig2_hdr_mode.0=1
-ipv6_lpm_128b_enable.0=2
-l2xmsg_mode.0=1
-max_vp_lags.0=0
-mdio_output_delay=0x0d
-miim_intr_enable.0=0
-module_64ports.0=0
-os=unix
 pbmp_oversubscribe.0=0x1fffffffffffffffffffffffffe
 pbmp_xport_xe.0=0x1fffffffffffffffffffffffffe
 phy_an_c37_1.0=3
@@ -243,10 +277,6 @@ serdes_firmware_mode_101.0=2
 serdes_firmware_mode_102.0=2
 serdes_firmware_mode_103.0=2
 serdes_firmware_mode_104.0=2
-stable_size=0x2000000
-tdma_timeout_usec.0=15000000
-tslam_timeout_usec.0=15000000
-xgxs_lcpll_xtal_refclk.0=1
 xgxs_rx_lane_map_1.0=0x3210
 xgxs_rx_lane_map_5.0=0x0321
 xgxs_rx_lane_map_9.0=0x1302