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[Buffer] Separate buffer profile for Arista-7260CX3-Q64

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Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
This commit is contained in:
Kevin Wang 2022-04-28 17:21:46 +08:00 committed by Ying Xie
parent a62af01e9e
commit 7566032403
10 changed files with 20 additions and 128 deletions
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1
device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/BALANCED Symbolic link
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../../../common/profiles/th2/7260/BALANCED

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/RDMA-CENTRIC Symbolic link
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../../../common/profiles/th2/7260/RDMA-CENTRIC

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/TCP-CENTRIC Symbolic link
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../../../common/profiles/th2/7260/TCP-CENTRIC

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffer_ports_t0.j2 Normal file
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffer_ports_t1.j2 Normal file
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{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffers_defaults_t0.j2
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{%- set default_cable = '5m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- import 'buffers_pool_sizes_t0.j2' as defs with context %}
{%- set ingress_lossless_pool_size = defs.ingress_lossless_pool_size %}
{%- set egress_lossy_pool_size = defs.egress_lossy_pool_size %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "{{ ingress_lossless_pool_size }}",
"type": "ingress",
"mode": "dynamic",
"xoff": "7827456"
},
"egress_lossy_pool": {
"size": "{{ egress_lossy_pool_size }}",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "42349632",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"ingress_lossless_pool",
"size":"0",
"static_th":"44302336"
},
"egress_lossless_profile": {
"pool":"egress_lossless_pool",
"size":"0",
"static_th":"42349632"
},
"egress_lossy_profile": {
"pool":"egress_lossy_pool",
"size":"1664",
"dynamic_th":"-1"
}
},
{%- endmacro %}
{% import 'buffers_extra_queues.j2' as defs with context %}
{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %}
{{ defs.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }}
{%- endmacro %}

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffers_defaults_t0.j2 Symbolic link
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BALANCED/buffers_defaults_t0.j2

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffers_defaults_t1.j2
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{%- set default_cable = '300m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,64) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- import 'buffers_pool_sizes_t0.j2' as defs with context %}
{%- set ingress_lossless_pool_size = defs.ingress_lossless_pool_size %}
{%- set egress_lossy_pool_size = defs.egress_lossy_pool_size %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "{{ ingress_lossless_pool_size }}",
"type": "ingress",
"mode": "dynamic",
"xoff": "7827456"
},
"egress_lossy_pool": {
"size": "{{ egress_lossy_pool_size }}",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "42349632",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"ingress_lossless_pool",
"size":"0",
"static_th":"44302336"
},
"egress_lossless_profile": {
"pool":"egress_lossless_pool",
"size":"0",
"static_th":"42349632"
},
"egress_lossy_profile": {
"pool":"egress_lossy_pool",
"size":"1664",
"dynamic_th":"-1"
}
},
{%- endmacro %}
{% import 'buffers_extra_queues.j2' as defs1 with context %}
{% import 'buffers_extra_pgs.j2' as defs2 with context %}
{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %}
{{ defs1.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }}
{%- endmacro %}
{%- macro generate_pg_buffers_with_extra_lossy_pgs(port_names, port_names_require_no_extra_pgs) %}
{{ defs2.generate_pg_buffers_with_extra_lossy_pgs(port_names, port_names_require_no_extra_pgs) }}
{%- endmacro %}

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffers_defaults_t1.j2 Symbolic link
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BALANCED/buffers_defaults_t1.j2

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/buffers_pool_sizes_t1.j2 Symbolic link
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../Arista-7260CX3-C64/buffers_pool_sizes_t1.j2

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/pg_profile_lookup.ini
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# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
40000 5m 1248 1248 56160 -3 2496
50000 5m 1248 1248 56160 -3 2496
100000 5m 1248 1248 96928 -3 2496
40000 40m 1248 1248 71552 -3 2496
50000 40m 1248 1248 96096 -3 2496
100000 40m 1248 1248 177632 -3 2496
40000 300m 1248 1248 108160 -3 2496
50000 300m 1248 1248 141856 -3 2496
100000 300m 1248 1248 268736 -3 2496

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/pg_profile_lookup.ini Symbolic link
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BALANCED/pg_profile_lookup.ini

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device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/qos.json.j2
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../Arista-7260CX3-C64/qos.json.j2 BALANCED/qos.json.j2