[device/dell] Add z9100 pfc T0 support (#1708)
This commit adds new code to support z9100 PFC T0 support with broadcom recommended MMU settings for PFC feature. Unit tested the setting by loading sonic-broadcom.bin and checking the hardware for the values from the JSON file. The T0 configs supports fan-out of 100G ports on Z9100. Added new config.bcm for fanout of 100G ports and tested the fanout by sending traffic using bcmcmd, new config.bcm file will be copied to /usr/share/sonic/hwsku/th-z9100-8x100-48x50G.config.bcm. The sai.profile file is updated to point to hwsku directory. Signed-off-by: Harish Venkatraman <Harish_Venkatraman@dell.com>
This commit is contained in:
Harish Venkatraman
Ying Xie
parent
46dc46e110
commit
5feb3632c9
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{%- set default_topo = 't0' %}
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{%- include 'buffers_config.j2' %}
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{%- set default_cable = '5m' %}
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{%- macro generate_port_lists(PORT_ALL) %}
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{# Generate list of ports #}
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{%- for port_idx in range(0,6) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
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{%- endfor %}
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{%- for port_idx in range(10,26) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
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{%- endfor %}
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{%- for port_idx in range(30,32) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4 + 2)) %}{%- endif %}
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{%- endfor %}
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{%- for port_idx in range(6,10) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- endfor %}
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{%- for port_idx in range(26,30) %}
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{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
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{%- endfor %}
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{%- endmacro %}
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{%- macro generate_buffer_pool_and_profiles() %}
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"BUFFER_POOL": {
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"ingress_lossless_pool": {
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"size": "11213696",
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"type": "ingress",
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"mode": "dynamic",
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"xoff": "8356608"
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},
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"egress_lossy_pool": {
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"size": "9532224",
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"type": "egress",
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"mode": "dynamic"
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},
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"egress_lossless_pool": {
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"size": "15982720",
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"type": "egress",
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"mode": "static"
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}
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},
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"BUFFER_PROFILE": {
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"ingress_lossy_profile": {
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"pool":"[BUFFER_POOL|ingress_lossless_pool]",
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"size":"0",
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"dynamic_th":"3"
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},
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"egress_lossless_profile": {
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"pool":"[BUFFER_POOL|egress_lossless_pool]",
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"size":"1518",
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"static_th":"3995680"
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},
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"egress_lossy_profile": {
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"pool":"[BUFFER_POOL|egress_lossy_pool]",
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"size":"1518",
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"dynamic_th":"3"
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}
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},
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{%- endmacro %}
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# PG lossless profiles.
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# speed cable size xon xoff threshold xon_offset
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10000 5m 1248 2288 35776 -4 2288
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25000 5m 1248 2288 53248 -4 2288
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40000 5m 1248 2288 66560 -4 2288
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50000 5m 1248 2288 79872 -4 2288
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100000 5m 1248 2288 165568 -4 2288
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10000 40m 1248 2288 37024 -4 2288
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25000 40m 1248 2288 56160 -4 2288
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40000 40m 1248 2288 71552 -4 2288
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50000 40m 1248 2288 85696 -4 2288
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100000 40m 1248 2288 177632 -4 2288
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10000 300m 1248 2288 46176 -4 2288
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25000 300m 1248 2288 79040 -4 2288
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40000 300m 1248 2288 108160 -4 2288
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50000 300m 1248 2288 131456 -4 2288
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100000 300m 1248 2288 268736 -4 2288
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# name lanes alias index speed
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Ethernet0 49,50 fiftyGigE1/1/1 1 50000
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Ethernet2 51,52 fiftyGigE1/1/2 1 50000
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Ethernet4 53,54 fiftyGigE1/2/1 2 50000
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Ethernet6 55,56 fiftyGigE1/2/2 2 50000
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Ethernet8 57,58 fiftyGigE1/3/1 3 50000
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Ethernet10 59,60 fiftyGigE1/3/2 3 50000
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Ethernet12 61,62 fiftyGigE1/4/1 4 50000
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Ethernet14 63,64 fiftyGigE1/4/2 4 50000
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Ethernet16 65,66 fiftyGigE1/5/1 5 50000
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Ethernet18 67,68 fiftyGigE1/5/2 5 50000
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Ethernet20 69,70 fiftyGigE1/6/1 6 50000
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Ethernet22 71,72 fiftyGigE1/6/2 6 50000
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Ethernet24 73,74,75,76 hundredGigE1/7 7 100000
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Ethernet28 77,78,79,80 hundredGigE1/8 8 100000
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Ethernet32 37,38,39,40 hundredGigE1/9 9 100000
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Ethernet36 33,34,35,36 hundredGigE1/10 10 100000
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Ethernet40 45,46 fiftyGigE1/11/1 11 50000
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Ethernet42 47,48 fiftyGigE1/11/2 11 50000
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Ethernet44 41,42 fiftyGigE1/12/1 12 50000
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Ethernet46 43,44 fiftyGigE1/12/2 12 50000
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Ethernet48 81,82 fiftyGigE1/13/1 13 50000
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Ethernet50 83,84 fiftyGigE1/13/2 13 50000
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Ethernet52 85,86 fiftyGigE1/14/1 14 50000
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Ethernet54 87,88 fiftyGigE1/14/2 14 50000
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Ethernet56 89,90 fiftyGigE1/15/1 15 50000
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Ethernet58 91,92 fiftyGigE1/15/2 15 50000
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Ethernet60 93,94 fiftyGigE1/16/1 16 50000
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Ethernet62 95,96 fiftyGigE1/16/2 16 50000
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Ethernet64 97,98 fiftyGigE1/17/1 17 50000
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Ethernet66 99,100 fiftyGigE1/17/2 17 50000
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Ethernet68 101,102 fiftyGigE1/18/1 18 50000
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Ethernet70 103,104 fiftyGigE1/18/2 18 50000
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Ethernet72 105,106 fiftyGigE1/19/1 19 50000
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Ethernet74 107,108 fiftyGigE1/19/2 19 50000
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Ethernet76 109,110 fiftyGigE1/20/1 20 50000
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Ethernet78 111,112 fiftyGigE1/20/2 20 50000
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Ethernet80 21,22 fiftyGigE1/21/1 21 50000
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Ethernet82 23,24 fiftyGigE1/21/2 21 50000
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Ethernet84 17,18 fiftyGigE1/22/1 22 50000
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Ethernet86 19,20 fiftyGigE1/22/2 22 50000
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Ethernet88 29,30 fiftyGigE1/23/1 23 50000
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Ethernet90 31,32 fiftyGigE1/23/2 23 50000
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Ethernet92 25,26 fiftyGigE1/24/1 24 50000
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Ethernet94 27,28 fiftyGigE1/24/2 24 50000
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Ethernet96 117,118 fiftyGigE1/25/1 25 50000
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Ethernet98 119,120 fiftyGigE1/25/2 25 50000
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Ethernet100 113,114 fiftyGigE1/26/1 26 50000
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Ethernet102 115,116 fiftyGigE1/26/2 26 50000
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Ethernet104 125,126,127,128 hundredGigE1/27 27 100000
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Ethernet108 121,122,123,124 hundredGigE1/28 28 100000
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Ethernet112 5,6,7,8 hundredGigE1/29 29 100000
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Ethernet116 1,2,3,4 hundredGigE1/30 30 100000
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Ethernet120 13,14 fiftyGigE1/31/1 31 50000
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Ethernet122 15,16 fiftyGigE1/31/2 31 50000
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Ethernet124 9,10 fiftyGigE1/32/1 32 50000
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Ethernet126 11,12 fiftyGigE1/32/2 32 50000
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167
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100-T0/qos.json
Normal file
167
device/dell/x86_64-dell_z9100_c2538-r0/Force10-Z9100-T0/qos.json
Normal file
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{
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"TC_TO_PRIORITY_GROUP_MAP": {
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"AZURE": {
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"0": "0",
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"1": "1",
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"2": "2",
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"3": "3",
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"4": "4",
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"5": "5",
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"6": "6",
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"7": "7"
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}
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},
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"MAP_PFC_PRIORITY_TO_QUEUE": {
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"AZURE": {
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"0": "0",
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"1": "1",
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"2": "2",
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"3": "3",
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"4": "4",
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"5": "5",
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"6": "6",
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"7": "7"
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}
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},
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"TC_TO_QUEUE_MAP": {
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"AZURE": {
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"0": "0",
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"1": "1",
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"2": "2",
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"3": "3",
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"4": "4",
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"5": "5",
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"6": "6",
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"7": "7"
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}
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},
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"DSCP_TO_TC_MAP": {
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"AZURE": {
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"0":"0",
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"1":"0",
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"2":"0",
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"3":"3",
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"4":"4",
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"5":"0",
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"6":"0",
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"7":"0",
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"8":"1",
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"9":"0",
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"10":"0",
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"11":"0",
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"12":"0",
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"13":"0",
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"14":"0",
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"15":"0",
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"16":"0",
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"17":"0",
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"18":"0",
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"19":"0",
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"20":"0",
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"21":"0",
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"22":"0",
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"23":"0",
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"24":"0",
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"25":"0",
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"26":"0",
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"27":"0",
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"28":"0",
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"29":"0",
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"30":"0",
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"31":"0",
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"32":"0",
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"33":"0",
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"34":"0",
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"35":"0",
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"36":"0",
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"37":"0",
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"38":"0",
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"39":"0",
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"40":"0",
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"41":"0",
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"42":"0",
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"43":"0",
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"44":"0",
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"45":"0",
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"46":"0",
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"47":"0",
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"48":"0",
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"49":"0",
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"50":"0",
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"51":"0",
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"52":"0",
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"53":"0",
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"54":"0",
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"55":"0",
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"56":"0",
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"57":"0",
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"58":"0",
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"59":"0",
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"60":"0",
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"61":"0",
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"62":"0",
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"63":"0"
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}
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},
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"SCHEDULER": {
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"scheduler.0" : {
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"type":"DWRR",
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"weight": "25"
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},
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"scheduler.1" : {
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"type":"DWRR",
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"weight": "30"
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},
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"scheduler.2" : {
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"type":"DWRR",
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"weight": "20"
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}
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},
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"PORT_QOS_MAP": {
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"Ethernet0,Ethernet2,Ethernet4,Ethernet6,Ethernet8,Ethernet10,Ethernet12,Ethernet14,Ethernet16,Ethernet18,Ethernet20,Ethernet22,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet40,Ethernet42,Ethernet44,Ethernet46,Ethernet48,Ethernet50,Ethernet52,Ethernet54,Ethernet56,Ethernet58,Ethernet60,Ethernet62,Ethernet64,Ethernet66,Ethernet68,Ethernet70,Ethernet72,Ethernet74,Ethernet76,Ethernet78,Ethernet80,Ethernet82,Ethernet84,Ethernet86,Ethernet88,Ethernet90,Ethernet92,Ethernet94,Ethernet96,Ethernet98,Ethernet100,Ethernet102,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet120,Ethernet122,Ethernet124,Ethernet126": {
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"dscp_to_tc_map" : "[DSCP_TO_TC_MAP|AZURE]",
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"tc_to_queue_map" : "[TC_TO_QUEUE_MAP|AZURE]",
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"tc_to_pg_map" : "[TC_TO_PRIORITY_GROUP_MAP|AZURE]",
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"pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|AZURE]",
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"pfc_enable": "3,4"
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}
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},
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"WRED_PROFILE": {
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"AZURE_LOSSY" : {
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"wred_green_enable":"true",
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"wred_yellow_enable":"true",
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"ecn":"ecn_all",
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"red_max_threshold":"512000",
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"red_min_threshold":"512000",
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"yellow_max_threshold":"512000",
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"yellow_min_threshold":"512000",
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"green_max_threshold": "184320",
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"green_min_threshold": "184320"
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},
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"AZURE_LOSSLESS" : {
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"wred_green_enable":"true",
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"wred_yellow_enable":"true",
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"ecn":"ecn_all",
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"red_max_threshold":"512000",
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"red_min_threshold":"512000",
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"yellow_max_threshold":"512000",
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"yellow_min_threshold":"512000",
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"green_max_threshold": "184320",
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"green_min_threshold": "184320"
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}
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},
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"QUEUE": {
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"Ethernet0,Ethernet2,Ethernet4,Ethernet6,Ethernet8,Ethernet10,Ethernet12,Ethernet14,Ethernet16,Ethernet18,Ethernet20,Ethernet22,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet40,Ethernet42,Ethernet44,Ethernet46,Ethernet48,Ethernet50,Ethernet52,Ethernet54,Ethernet56,Ethernet58,Ethernet60,Ethernet62,Ethernet64,Ethernet66,Ethernet68,Ethernet70,Ethernet72,Ethernet74,Ethernet76,Ethernet78,Ethernet80,Ethernet82,Ethernet84,Ethernet86,Ethernet88,Ethernet90,Ethernet92,Ethernet94,Ethernet96,Ethernet98,Ethernet100,Ethernet102,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet120,Ethernet122,Ethernet124,Ethernet126|0-1": {
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"wred_profile" : "[WRED_PROFILE|AZURE_LOSSY]"
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},
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"Ethernet0,Ethernet2,Ethernet4,Ethernet6,Ethernet8,Ethernet10,Ethernet12,Ethernet14,Ethernet16,Ethernet18,Ethernet20,Ethernet22,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet40,Ethernet42,Ethernet44,Ethernet46,Ethernet48,Ethernet50,Ethernet52,Ethernet54,Ethernet56,Ethernet58,Ethernet60,Ethernet62,Ethernet64,Ethernet66,Ethernet68,Ethernet70,Ethernet72,Ethernet74,Ethernet76,Ethernet78,Ethernet80,Ethernet82,Ethernet84,Ethernet86,Ethernet88,Ethernet90,Ethernet92,Ethernet94,Ethernet96,Ethernet98,Ethernet100,Ethernet102,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet120,Ethernet122,Ethernet124,Ethernet126|3-4": {
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"scheduler" : "[SCHEDULER|scheduler.0]"
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},
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||||||
|
"Ethernet0,Ethernet2,Ethernet4,Ethernet6,Ethernet8,Ethernet10,Ethernet12,Ethernet14,Ethernet16,Ethernet18,Ethernet20,Ethernet22,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet40,Ethernet42,Ethernet44,Ethernet46,Ethernet48,Ethernet50,Ethernet52,Ethernet54,Ethernet56,Ethernet58,Ethernet60,Ethernet62,Ethernet64,Ethernet66,Ethernet68,Ethernet70,Ethernet72,Ethernet74,Ethernet76,Ethernet78,Ethernet80,Ethernet82,Ethernet84,Ethernet86,Ethernet88,Ethernet90,Ethernet92,Ethernet94,Ethernet96,Ethernet98,Ethernet100,Ethernet102,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet120,Ethernet122,Ethernet124,Ethernet126|0": {
|
||||||
|
"scheduler" : "[SCHEDULER|scheduler.1]"
|
||||||
|
},
|
||||||
|
"Ethernet0,Ethernet2,Ethernet4,Ethernet6,Ethernet8,Ethernet10,Ethernet12,Ethernet14,Ethernet16,Ethernet18,Ethernet20,Ethernet22,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet40,Ethernet42,Ethernet44,Ethernet46,Ethernet48,Ethernet50,Ethernet52,Ethernet54,Ethernet56,Ethernet58,Ethernet60,Ethernet62,Ethernet64,Ethernet66,Ethernet68,Ethernet70,Ethernet72,Ethernet74,Ethernet76,Ethernet78,Ethernet80,Ethernet82,Ethernet84,Ethernet86,Ethernet88,Ethernet90,Ethernet92,Ethernet94,Ethernet96,Ethernet98,Ethernet100,Ethernet102,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet120,Ethernet122,Ethernet124,Ethernet126|1": {
|
||||||
|
"scheduler" : "[SCHEDULER|scheduler.2]"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -0,0 +1 @@
|
|||||||
|
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-z9100-8x100G-48x50G.config.bcm
|
||||||
@ -0,0 +1,377 @@
|
|||||||
|
phy_xaui_rx_polarity_flip_103.0=0x0
|
||||||
|
phy_xaui_tx_polarity_flip_9.0=0x3
|
||||||
|
dport_map_port_72.0=21
|
||||||
|
dport_map_port_46.0=41
|
||||||
|
xgxs_rx_lane_map_102.0=0x3201
|
||||||
|
xgxs_rx_lane_map_103.0=0x3201
|
||||||
|
xgxs_tx_lane_map_110.0=0x132
|
||||||
|
xgxs_tx_lane_map_111.0=0x132
|
||||||
|
portmap_55.0=55:50:2
|
||||||
|
portmap_29.0=29:50:2
|
||||||
|
portmap_102.0=97:50:2
|
||||||
|
dport_map_port_55.0=6
|
||||||
|
l2xmsg_hostbuf_size.0=8192
|
||||||
|
l3_mem_entries.0=73728
|
||||||
|
dport_map_port_29.0=89
|
||||||
|
portmap_10.0=11:50:2
|
||||||
|
xgxs_rx_lane_map_68.0=0x3201
|
||||||
|
xgxs_tx_lane_map_68.0=0x3210
|
||||||
|
xgxs_rx_lane_map_69.0=0x3201
|
||||||
|
xgxs_tx_lane_map_69.0=0x3210
|
||||||
|
dport_map_port_119.0=102
|
||||||
|
portmap_38.0=37:100
|
||||||
|
dport_map_port_10.0=126
|
||||||
|
portmap_111.0=107:50:2
|
||||||
|
dport_map_port_38.0=33
|
||||||
|
phy_xaui_tx_polarity_flip_119.0=0x0
|
||||||
|
dport_map_port_100.0=130
|
||||||
|
module_64ports.0=0
|
||||||
|
portmap_73.0=71:50:2
|
||||||
|
xgxs_tx_lane_map_102.0=0x123
|
||||||
|
xgxs_tx_lane_map_103.0=0x123
|
||||||
|
portmap_47.0=47:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_69.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_100.0=0x6
|
||||||
|
phy_xaui_rx_polarity_flip_130.0=0x4
|
||||||
|
dport_map_port_73.0=22
|
||||||
|
dport_map_port_47.0=42
|
||||||
|
phy_xaui_rx_polarity_flip_50.0=0x0
|
||||||
|
phy_xaui_tx_polarity_flip_92.0=0x1
|
||||||
|
phy_xaui_tx_polarity_flip_66.0=0x6
|
||||||
|
portmap_5.0=5:100
|
||||||
|
portmap_103.0=99:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_21.0=0x3
|
||||||
|
tdma_intr_enable.0=1
|
||||||
|
phy_xaui_rx_polarity_flip_122.0=0x0
|
||||||
|
ipv6_lpm_128b_enable.0=0
|
||||||
|
xgxs_rx_lane_map_50.0=0x1023
|
||||||
|
xgxs_tx_lane_map_50.0=0x132
|
||||||
|
xgxs_rx_lane_map_51.0=0x1023
|
||||||
|
xgxs_tx_lane_map_51.0=0x132
|
||||||
|
phy_xaui_tx_polarity_flip_30.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_42.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_84.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_96.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_58.0=0x2
|
||||||
|
stat_if_parity_enable.0=1
|
||||||
|
dport_map_port_110.0=73
|
||||||
|
phy_xaui_rx_polarity_flip_51.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_13.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_25.0=0x2
|
||||||
|
oversubscribe_mode=1
|
||||||
|
xgxs_rx_lane_map_130.0=0x1023
|
||||||
|
phy_xaui_tx_polarity_flip_93.0=0x1
|
||||||
|
phy_xaui_tx_polarity_flip_110.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_114.0=0x0
|
||||||
|
portmap_130.0=125:100
|
||||||
|
xgxs_rx_lane_map_42.0=0x3210
|
||||||
|
xgxs_tx_lane_map_42.0=0x132
|
||||||
|
xgxs_rx_lane_map_43.0=0x3210
|
||||||
|
xgxs_tx_lane_map_43.0=0x132
|
||||||
|
phy_xaui_tx_polarity_flip_22.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_34.0=0xa
|
||||||
|
xgxs_rx_lane_map_96.0=0x3210
|
||||||
|
xgxs_tx_lane_map_96.0=0x123
|
||||||
|
xgxs_rx_lane_map_97.0=0x3210
|
||||||
|
xgxs_tx_lane_map_97.0=0x123
|
||||||
|
portmap_92.0=89:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_76.0=0x0
|
||||||
|
portmap_66.0=129:10
|
||||||
|
phy_xaui_rx_polarity_flip_88.0=0x1
|
||||||
|
phy_xaui_tx_polarity_flip_1.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_123.0=0x3
|
||||||
|
bcm_tunnel_term_compatible_mode.0=1
|
||||||
|
dport_map_port_92.0=57
|
||||||
|
dport_map_port_66.0=129
|
||||||
|
xgxs_rx_lane_map_25.0=0x2310
|
||||||
|
xgxs_tx_lane_map_25.0=0x2130
|
||||||
|
xgxs_rx_lane_map_26.0=0x2310
|
||||||
|
xgxs_tx_lane_map_26.0=0x2130
|
||||||
|
dport_map_port_102.0=65
|
||||||
|
portmap_21.0=21:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_43.0=0x3
|
||||||
|
table_dma_enable.0=1
|
||||||
|
phy_xaui_rx_polarity_flip_17.0=0x1
|
||||||
|
xgxs_rx_lane_map_122.0=0x3201
|
||||||
|
xgxs_rx_lane_map_123.0=0x3201
|
||||||
|
phy_xaui_tx_polarity_flip_85.0=0x1
|
||||||
|
xgxs_tx_lane_map_130.0=0x132
|
||||||
|
phy_xaui_rx_polarity_flip_97.0=0x2
|
||||||
|
phy_xaui_tx_polarity_flip_59.0=0x2
|
||||||
|
dport_map_port_21.0=81
|
||||||
|
phy_xaui_tx_polarity_flip_102.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_106.0=0x1
|
||||||
|
portmap_122.0=117:50:2
|
||||||
|
xgxs_rx_lane_map_34.0=0x1302
|
||||||
|
xgxs_tx_lane_map_34.0=0x2031
|
||||||
|
dport_map_port_111.0=74
|
||||||
|
portmap_30.0=31:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_14.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_26.0=0x0
|
||||||
|
xgxs_rx_lane_map_88.0=0x213
|
||||||
|
xgxs_rx_lane_map_89.0=0x213
|
||||||
|
dport_map_port_9.0=125
|
||||||
|
xgxs_tx_lane_map_88.0=0x1032
|
||||||
|
xgxs_tx_lane_map_89.0=0x1032
|
||||||
|
xgxs_tx_lane_map_5.0=0x213
|
||||||
|
portmap_84.0=81:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_68.0=0x2
|
||||||
|
portmap_58.0=57:50:2
|
||||||
|
dport_map_port_30.0=90
|
||||||
|
phy_xaui_tx_polarity_flip_111.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_115.0=0x0
|
||||||
|
dport_map_port_84.0=49
|
||||||
|
dport_map_port_58.0=9
|
||||||
|
xgxs_rx_lane_map_17.0=0x2103
|
||||||
|
xgxs_tx_lane_map_17.0=0x3102
|
||||||
|
xgxs_rx_lane_map_18.0=0x2103
|
||||||
|
xgxs_tx_lane_map_18.0=0x3102
|
||||||
|
portmap_13.0=13:50:2
|
||||||
|
xgxs_rx_lane_map_114.0=0x3210
|
||||||
|
xgxs_rx_lane_map_115.0=0x3210
|
||||||
|
portmap_93.0=91:50:2
|
||||||
|
xgxs_tx_lane_map_122.0=0x2310
|
||||||
|
xgxs_tx_lane_map_123.0=0x2310
|
||||||
|
phy_xaui_rx_polarity_flip_89.0=0x3
|
||||||
|
dport_map_port_13.0=121
|
||||||
|
schan_intr_enable.0=0
|
||||||
|
portmap_114.0=109:50:2
|
||||||
|
dport_map_port_93.0=58
|
||||||
|
dport_map_port_103.0=66
|
||||||
|
portmap_22.0=23:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_18.0=0x1
|
||||||
|
xgxs_rx_lane_map_5.0=0x1203
|
||||||
|
portmap_76.0=73:100
|
||||||
|
phy_xaui_rx_polarity_flip_5.0=0x7
|
||||||
|
dport_map_port_22.0=82
|
||||||
|
phy_xaui_tx_polarity_flip_103.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_107.0=0x3
|
||||||
|
portmap_123.0=119:50:2
|
||||||
|
os.0=unix
|
||||||
|
dport_map_port_76.0=25
|
||||||
|
parity_enable.0=1
|
||||||
|
xgxs_rx_lane_map_106.0=0x213
|
||||||
|
xgxs_rx_lane_map_107.0=0x213
|
||||||
|
portmap_85.0=83:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_69.0=0x0
|
||||||
|
xgxs_tx_lane_map_114.0=0x123
|
||||||
|
xgxs_tx_lane_map_115.0=0x123
|
||||||
|
portmap_59.0=59:50:2
|
||||||
|
pbmp_oversubscribe.0=0x3fffffffdffffffff7fffffffdfffffffe
|
||||||
|
portmap_106.0=101:50:2
|
||||||
|
dport_map_port_85.0=50
|
||||||
|
dport_map_port_59.0=10
|
||||||
|
tdma_timeout_usec=1000000
|
||||||
|
phy_xaui_tx_polarity_flip_50.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_62.0=0x3
|
||||||
|
portmap_14.0=15:50:2
|
||||||
|
portmap_68.0=65:50:2
|
||||||
|
dport_map_port_14.0=122
|
||||||
|
portmap_115.0=111:50:2
|
||||||
|
dport_map_port_68.0=17
|
||||||
|
dport_map_port_130.0=105
|
||||||
|
xgxs_tx_lane_map_106.0=0x123
|
||||||
|
xgxs_tx_lane_map_107.0=0x123
|
||||||
|
lls_num_l2uc.0=10
|
||||||
|
phy_xaui_tx_polarity_flip_130.0=0xb
|
||||||
|
os=unix
|
||||||
|
xgxs_rx_lane_map_62.0=0x1302
|
||||||
|
xgxs_tx_lane_map_62.0=0x3201
|
||||||
|
xgxs_rx_lane_map_63.0=0x1302
|
||||||
|
xgxs_tx_lane_map_63.0=0x3201
|
||||||
|
phy_xaui_rx_polarity_flip_80.0=0xd
|
||||||
|
phy_xaui_tx_polarity_flip_42.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_54.0=0x1
|
||||||
|
phy_xaui_tx_polarity_flip_96.0=0x0
|
||||||
|
miim_intr_enable.0=0
|
||||||
|
portmap_9.0=9:50:2
|
||||||
|
portmap_107.0=103:50:2
|
||||||
|
dport_map_port_122.0=97
|
||||||
|
phy_xaui_tx_polarity_flip_51.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_63.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_25.0=0x2
|
||||||
|
portmap_69.0=67:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_122.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_126.0=0x7
|
||||||
|
xgxs_rx_lane_map_80.0=0x2301
|
||||||
|
dport_map_port_69.0=18
|
||||||
|
xgxs_rx_lane_map_54.0=0x1302
|
||||||
|
xgxs_rx_lane_map_55.0=0x1302
|
||||||
|
dport_map_port_1.0=117
|
||||||
|
xgxs_tx_lane_map_80.0=0x1320
|
||||||
|
xgxs_tx_lane_map_54.0=0x2301
|
||||||
|
xgxs_tx_lane_map_55.0=0x2301
|
||||||
|
table_dma_enable=1
|
||||||
|
portmap_50.0=49:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_72.0=0x2
|
||||||
|
phy_xaui_tx_polarity_flip_34.0=0xb
|
||||||
|
phy_xaui_rx_polarity_flip_46.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_88.0=0x3
|
||||||
|
dport_map_port_50.0=1
|
||||||
|
l2_mem_entries.0=73728
|
||||||
|
l2xmsg_mode.0=1
|
||||||
|
dport_map_port_114.0=77
|
||||||
|
phy_xaui_tx_polarity_flip_43.0=0x1
|
||||||
|
phy_xaui_rx_polarity_flip_55.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_17.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_29.0=0x0
|
||||||
|
phy_xaui_tx_polarity_flip_97.0=0x2
|
||||||
|
phy_xaui_tx_polarity_flip_114.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_118.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_10.0=0x2
|
||||||
|
xgxs_rx_lane_map_72.0=0x1302
|
||||||
|
xgxs_rx_lane_map_73.0=0x1302
|
||||||
|
xgxs_rx_lane_map_46.0=0x2103
|
||||||
|
xgxs_rx_lane_map_47.0=0x2103
|
||||||
|
xgxs_tx_lane_map_72.0=0x2301
|
||||||
|
xgxs_tx_lane_map_73.0=0x2301
|
||||||
|
xgxs_tx_lane_map_46.0=0x1023
|
||||||
|
xgxs_tx_lane_map_47.0=0x1023
|
||||||
|
dport_map_port_123.0=98
|
||||||
|
portmap_42.0=41:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_26.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_38.0=0xd
|
||||||
|
portmap_96.0=93:50:2
|
||||||
|
phy_xaui_tx_polarity_flip_5.0=0x8
|
||||||
|
dport_map_port_42.0=45
|
||||||
|
phy_xaui_tx_polarity_flip_123.0=0x3
|
||||||
|
dport_map_port_96.0=61
|
||||||
|
xgxs_rx_lane_map_29.0=0x2301
|
||||||
|
xgxs_tx_lane_map_29.0=0x1023
|
||||||
|
xgxs_rx_lane_map_30.0=0x2301
|
||||||
|
xgxs_tx_lane_map_30.0=0x1023
|
||||||
|
dport_map_port_106.0=69
|
||||||
|
portmap_51.0=51:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_73.0=0x0
|
||||||
|
portmap_25.0=25:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_47.0=0x1
|
||||||
|
xgxs_rx_lane_map_126.0=0x213
|
||||||
|
phy_xaui_tx_polarity_flip_89.0=0x3
|
||||||
|
dport_map_port_51.0=2
|
||||||
|
dport_map_port_25.0=93
|
||||||
|
phy_xaui_tx_polarity_flip_106.0=0x3
|
||||||
|
portmap_126.0=121:100
|
||||||
|
xgxs_rx_lane_map_38.0=0x312
|
||||||
|
xgxs_tx_lane_map_38.0=0x1032
|
||||||
|
dport_map_port_115.0=78
|
||||||
|
portmap_34.0=33:100
|
||||||
|
phy_xaui_tx_polarity_flip_18.0=0x3
|
||||||
|
pbmp_xport_xe.0=0x3fffffffdffffffff7fffffffdfffffffe
|
||||||
|
xgxs_tx_lane_map_9.0=0x123
|
||||||
|
xgxs_tx_lane_map_10.0=0x123
|
||||||
|
portmap_88.0=85:50:2
|
||||||
|
max_vp_lags.0=0
|
||||||
|
dport_map_port_34.0=37
|
||||||
|
phy_xaui_tx_polarity_flip_115.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_119.0=0x2
|
||||||
|
dport_map_port_88.0=53
|
||||||
|
portmap_43.0=43:50:2
|
||||||
|
portmap_17.0=17:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_100.0=0xf
|
||||||
|
xgxs_rx_lane_map_118.0=0x123
|
||||||
|
xgxs_rx_lane_map_119.0=0x123
|
||||||
|
portmap_97.0=95:50:2
|
||||||
|
xgxs_tx_lane_map_126.0=0x123
|
||||||
|
dport_map_port_43.0=46
|
||||||
|
dport_map_port_17.0=85
|
||||||
|
portmap_118.0=113:50:2
|
||||||
|
dport_map_port_97.0=62
|
||||||
|
num_ipv6_lpm_128b_entries.0=0
|
||||||
|
phy_xaui_tx_polarity_flip_62.0=0x3
|
||||||
|
dport_map_port_107.0=70
|
||||||
|
portmap_26.0=27:50:2
|
||||||
|
xgxs_rx_lane_map_9.0=0x213
|
||||||
|
xgxs_rx_lane_map_10.0=0x213
|
||||||
|
portmap_1.0=1:100
|
||||||
|
phy_xaui_rx_polarity_flip_9.0=0x0
|
||||||
|
dport_map_port_26.0=94
|
||||||
|
phy_xaui_tx_polarity_flip_107.0=0x3
|
||||||
|
portmap_89.0=87:50:2
|
||||||
|
xgxs_tx_lane_map_118.0=0x2013
|
||||||
|
xgxs_tx_lane_map_119.0=0x2013
|
||||||
|
dport_map_port_89.0=54
|
||||||
|
phy_xaui_tx_polarity_flip_80.0=0xa
|
||||||
|
phy_xaui_rx_polarity_flip_92.0=0x0
|
||||||
|
phy_xaui_tx_polarity_flip_54.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_66.0=0xf
|
||||||
|
portmap_18.0=19:50:2
|
||||||
|
dport_map_port_18.0=86
|
||||||
|
portmap_119.0=115:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_21.0=0x0
|
||||||
|
xgxs_rx_lane_map_100.0=0x3210
|
||||||
|
phy_xaui_tx_polarity_flip_63.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_110.0=0x3
|
||||||
|
portmap_100.0=131:10
|
||||||
|
phy_xaui_rx_polarity_flip_30.0=0x0
|
||||||
|
xgxs_rx_lane_map_92.0=0x3210
|
||||||
|
xgxs_rx_lane_map_93.0=0x3210
|
||||||
|
xgxs_rx_lane_map_66.0=0x3210
|
||||||
|
xgxs_tx_lane_map_92.0=0x132
|
||||||
|
xgxs_tx_lane_map_93.0=0x132
|
||||||
|
xgxs_tx_lane_map_66.0=0x132
|
||||||
|
phy_xaui_tx_polarity_flip_72.0=0x0
|
||||||
|
portmap_62.0=61:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_84.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_46.0=0x2
|
||||||
|
phy_xaui_rx_polarity_flip_58.0=0x2
|
||||||
|
tdma_intr_enable=1
|
||||||
|
dport_map_port_62.0=13
|
||||||
|
xgxs_rx_lane_map_21.0=0x3102
|
||||||
|
xgxs_rx_lane_map_22.0=0x3102
|
||||||
|
xgxs_tx_lane_map_21.0=0x132
|
||||||
|
xgxs_tx_lane_map_22.0=0x132
|
||||||
|
phy_xaui_rx_polarity_flip_13.0=0x0
|
||||||
|
tdma_timeout_usec.0=5000000
|
||||||
|
dport_map_port_126.0=109
|
||||||
|
phy_xaui_rx_polarity_flip_93.0=0x1
|
||||||
|
phy_xaui_tx_polarity_flip_55.0=0x0
|
||||||
|
xgxs_tx_lane_map_100.0=0x132
|
||||||
|
phy_xaui_tx_polarity_flip_29.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_102.0=0x2
|
||||||
|
parity_correction.0=1
|
||||||
|
phy_xaui_tx_polarity_flip_126.0=0x7
|
||||||
|
phy_xaui_tx_polarity_flip_10.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_22.0=0x0
|
||||||
|
xgxs_rx_lane_map_84.0=0x2301
|
||||||
|
xgxs_rx_lane_map_85.0=0x2301
|
||||||
|
xgxs_rx_lane_map_58.0=0x1203
|
||||||
|
xgxs_rx_lane_map_59.0=0x1203
|
||||||
|
dport_map_port_5.0=113
|
||||||
|
xgxs_tx_lane_map_84.0=0x213
|
||||||
|
xgxs_tx_lane_map_85.0=0x213
|
||||||
|
xgxs_tx_lane_map_58.0=0x123
|
||||||
|
xgxs_tx_lane_map_59.0=0x123
|
||||||
|
mmu_lossless.0=0
|
||||||
|
xgxs_tx_lane_map_1.0=0x123
|
||||||
|
portmap_80.0=77:100
|
||||||
|
portmap_54.0=53:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_76.0=0x2
|
||||||
|
phy_xaui_tx_polarity_flip_38.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_111.0=0x3
|
||||||
|
dport_map_port_80.0=29
|
||||||
|
dport_map_port_54.0=5
|
||||||
|
xgxs_rx_lane_map_13.0=0x3201
|
||||||
|
xgxs_rx_lane_map_14.0=0x3201
|
||||||
|
xgxs_tx_lane_map_13.0=0x2301
|
||||||
|
xgxs_tx_lane_map_14.0=0x2301
|
||||||
|
xgxs_rx_lane_map_110.0=0x3210
|
||||||
|
xgxs_rx_lane_map_111.0=0x3210
|
||||||
|
phy_xaui_tx_polarity_flip_73.0=0x0
|
||||||
|
dport_map_port_118.0=101
|
||||||
|
portmap_63.0=63:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_85.0=0x3
|
||||||
|
phy_xaui_tx_polarity_flip_47.0=0x3
|
||||||
|
phy_xaui_rx_polarity_flip_59.0=0x0
|
||||||
|
portmap_110.0=105:50:2
|
||||||
|
dport_map_port_63.0=14
|
||||||
|
phy_xaui_tx_polarity_flip_118.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_14.0=0x3
|
||||||
|
xgxs_rx_lane_map_76.0=0x1203
|
||||||
|
xgxs_tx_lane_map_76.0=0x123
|
||||||
|
xgxs_rx_lane_map_1.0=0x213
|
||||||
|
portmap_72.0=69:50:2
|
||||||
|
portmap_46.0=45:50:2
|
||||||
|
phy_xaui_rx_polarity_flip_68.0=0x0
|
||||||
|
phy_xaui_rx_polarity_flip_1.0=0x9
|
||||||
|
|
||||||
|
mmu_init_config="MSFT-TH-Tier0"
|
||||||
Loading…
Reference in New Issue
Block a user