[device] various improvement for nephos devices (#3139)
Add fan control for as7116-54x Modify sfputil.py to support sfp insert and remove events for as7116-54x Modify port_config.nps to set port default admin down Modify port_config.ini for add speed attr Code format optimization like remove newline Modify buffers_defaults_t0 and t1, change ingress_lossless_pool mode from dynamic to static Add nephos_dac.nps and nephos_opt.nps for support difference dac and fiber module
This commit is contained in:
simonJi2018
lguohan
parent
c7db1ec2e2
commit
49f3b22de5
@ -19,7 +19,7 @@
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"ingress_lossless_pool": {
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"ingress_lossless_pool": {
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"size": "{{ ingress_lossless_pool_size }}",
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"size": "{{ ingress_lossless_pool_size }}",
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"type": "ingress",
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"type": "ingress",
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"mode": "dynamic"
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"mode": "static"
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},
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},
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"ingress_lossy_pool": {
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"ingress_lossy_pool": {
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"size": "{{ ingress_lossy_pool_size }}",
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"size": "{{ ingress_lossy_pool_size }}",
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@ -29,7 +29,7 @@
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"egress_lossless_pool": {
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"egress_lossless_pool": {
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"size": "{{ egress_lossless_pool_size }}",
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"size": "{{ egress_lossless_pool_size }}",
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"type": "egress",
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"type": "egress",
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"mode": "dynamic"
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"mode": "static"
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},
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},
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"egress_lossy_pool": {
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"egress_lossy_pool": {
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"size": "{{ egress_lossy_pool_size }}",
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"size": "{{ egress_lossy_pool_size }}",
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@ -19,7 +19,7 @@
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"ingress_lossless_pool": {
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"ingress_lossless_pool": {
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"size": "{{ ingress_lossless_pool_size }}",
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"size": "{{ ingress_lossless_pool_size }}",
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"type": "ingress",
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"type": "ingress",
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"mode": "dynamic"
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"mode": "static"
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},
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},
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"ingress_lossy_pool": {
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"ingress_lossy_pool": {
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"size": "{{ ingress_lossy_pool_size }}",
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"size": "{{ ingress_lossy_pool_size }}",
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@ -29,7 +29,7 @@
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"egress_lossless_pool": {
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"egress_lossless_pool": {
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"size": "{{ egress_lossless_pool_size }}",
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"size": "{{ egress_lossless_pool_size }}",
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"type": "egress",
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"type": "egress",
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"mode": "dynamic"
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"mode": "static"
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},
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},
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"egress_lossy_pool": {
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"egress_lossy_pool": {
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"size": "{{ egress_lossy_pool_size }}",
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"size": "{{ egress_lossy_pool_size }}",
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@ -0,0 +1,404 @@
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init start stage low-level
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init set port-map port=0 eth-macro=2 lane=0 max-speed=25g active=true
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init set port-map port=1 eth-macro=2 lane=1 max-speed=25g active=true
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init set port-map port=2 eth-macro=2 lane=2 max-speed=25g active=true
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init set port-map port=3 eth-macro=2 lane=3 max-speed=25g active=true
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init set port-map port=4 eth-macro=3 lane=0 max-speed=25g active=true
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init set port-map port=5 eth-macro=3 lane=1 max-speed=25g active=true
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init set port-map port=6 eth-macro=3 lane=2 max-speed=25g active=true
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init set port-map port=7 eth-macro=3 lane=3 max-speed=25g active=true
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init set port-map port=8 eth-macro=4 lane=0 max-speed=25g active=true
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init set port-map port=9 eth-macro=4 lane=1 max-speed=25g active=true
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init set port-map port=10 eth-macro=4 lane=2 max-speed=25g active=true
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init set port-map port=11 eth-macro=4 lane=3 max-speed=25g active=true
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init set port-map port=12 eth-macro=5 lane=0 max-speed=25g active=true
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init set port-map port=13 eth-macro=5 lane=1 max-speed=25g active=true
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init set port-map port=14 eth-macro=5 lane=2 max-speed=25g active=true
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init set port-map port=15 eth-macro=5 lane=3 max-speed=25g active=true
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init set port-map port=16 eth-macro=8 lane=0 max-speed=25g active=true
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init set port-map port=17 eth-macro=8 lane=1 max-speed=25g active=true
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init set port-map port=18 eth-macro=8 lane=2 max-speed=25g active=true
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init set port-map port=19 eth-macro=8 lane=3 max-speed=25g active=true
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init set port-map port=20 eth-macro=10 lane=0 max-speed=25g active=true
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init set port-map port=21 eth-macro=10 lane=1 max-speed=25g active=true
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init set port-map port=22 eth-macro=10 lane=2 max-speed=25g active=true
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init set port-map port=23 eth-macro=10 lane=3 max-speed=25g active=true
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init set port-map port=24 eth-macro=12 lane=0 max-speed=25g active=true
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init set port-map port=25 eth-macro=12 lane=1 max-speed=25g active=true
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init set port-map port=26 eth-macro=12 lane=2 max-speed=25g active=true
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init set port-map port=27 eth-macro=12 lane=3 max-speed=25g active=true
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init set port-map port=28 eth-macro=14 lane=0 max-speed=25g active=true
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init set port-map port=29 eth-macro=14 lane=1 max-speed=25g active=true
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init set port-map port=30 eth-macro=14 lane=2 max-speed=25g active=true
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init set port-map port=31 eth-macro=14 lane=3 max-speed=25g active=true
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init set port-map port=32 eth-macro=16 lane=0 max-speed=25g active=true
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init set port-map port=33 eth-macro=16 lane=1 max-speed=25g active=true
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init set port-map port=34 eth-macro=16 lane=2 max-speed=25g active=true
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init set port-map port=35 eth-macro=16 lane=3 max-speed=25g active=true
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init set port-map port=36 eth-macro=17 lane=0 max-speed=25g active=true
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init set port-map port=37 eth-macro=17 lane=1 max-speed=25g active=true
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init set port-map port=38 eth-macro=17 lane=2 max-speed=25g active=true
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init set port-map port=39 eth-macro=17 lane=3 max-speed=25g active=true
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init set port-map port=40 eth-macro=18 lane=0 max-speed=25g active=true
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init set port-map port=41 eth-macro=18 lane=1 max-speed=25g active=true
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init set port-map port=42 eth-macro=18 lane=2 max-speed=25g active=true
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init set port-map port=43 eth-macro=18 lane=3 max-speed=25g active=true
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init set port-map port=44 eth-macro=19 lane=0 max-speed=25g active=true
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init set port-map port=45 eth-macro=19 lane=1 max-speed=25g active=true
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init set port-map port=46 eth-macro=19 lane=2 max-speed=25g active=true
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init set port-map port=47 eth-macro=19 lane=3 max-speed=25g active=true
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init set port-map port=48 eth-macro=20 lane=0 max-speed=100g active=true
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init set port-map port=49 eth-macro=21 lane=0 max-speed=100g active=true
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init set port-map port=50 eth-macro=26 lane=0 max-speed=100g active=true
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init set port-map port=51 eth-macro=27 lane=0 max-speed=100g active=true
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init set port-map port=52 eth-macro=28 lane=0 max-speed=100g active=true
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init set port-map port=53 eth-macro=29 lane=0 max-speed=100g active=true
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init set port-map port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
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init set port-map port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
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init start stage task-rsrc
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init start stage module
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init start stage task
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phy set lane-swap portlist=0 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=1 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=2 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=3 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=4 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=5 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=6 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=7 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=8 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=9 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=10 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=11 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=12 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=13 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=14 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=15 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=16 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=17 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=18 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=19 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=20 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=21 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=22 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=23 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=24 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=25 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=26 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=27 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=28 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=29 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=30 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=31 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=32 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=33 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=34 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=35 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=36 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=37 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=38 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=39 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=40 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=41 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=42 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=43 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=44 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=45 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=46 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=47 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=48-53 lane-cnt=4 property=tx data=0x03.02.01.00
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phy set lane-swap portlist=0 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=1 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=2 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=3 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=4 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=5 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=6 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=7 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=8 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=9 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=10 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=11 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=12 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=13 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=14 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=15 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=16 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=17 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=18 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=19 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=20 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=21 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=22 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=23 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=24 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=25 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=26 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=27 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=28 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=29 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=30 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=31 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=32 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=33 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=34 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=35 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=36 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=37 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=38 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=39 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=40 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=41 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=42 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=43 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=44 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=45 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=46 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=47 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=48-53 lane-cnt=4 property=rx data=0x03.02.01.00
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phy set polarity-rev portlist=0 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=1 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=2 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=3 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=4 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=5 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=6 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=7 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=8 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=9 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=10 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=11 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=12 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=13 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=14 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=15 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=16 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=17 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=18 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=19 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=20 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=21 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=22 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=23 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=24 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=25 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=26 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=27 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=28 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=29 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=30 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=31 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=32 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=33 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=34 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=35 lane-cnt=1 property=tx data=0x0
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||||||
|
phy set polarity-rev portlist=36 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=37 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=38 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=39 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=40 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=41 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=42 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=43 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=44 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=45 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=46 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=47 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=0 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=1 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=2 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=3 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=4 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=5 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=6 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=7 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=8 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=9 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=10 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=11 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=12 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=13 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=14 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=15 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=16 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=17 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=18 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=19 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=20 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=21 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=22 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=23 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=24 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=25 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=26 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=27 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=28 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=29 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=30 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=31 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=32 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=33 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=34 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=35 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=36 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=37 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=38 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=39 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=40 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=41 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=42 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=43 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=44 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=45 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=46 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=47 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||||||
|
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=2 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=3 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=4 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=5 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=6 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=7 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=8 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=9 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=10 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=11 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=12 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=13 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=14 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=15 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=16 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=17 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=18 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=19 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=20 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=21 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=22 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=23 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=24 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=25 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=26 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=27 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=28 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=29 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=30 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=31 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=32 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=33 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=34 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=35 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=36 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=37 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=38 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=39 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=40 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=41 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=42 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=43 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=44 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=45 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=46 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=47 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=48 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=49 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=50 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=51 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=52 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=53 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=129 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=130 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
port set property portlist=0-47 speed=25g
|
||||||
|
port set property portlist=48-53 speed=100g
|
||||||
|
port set property portlist=129-130 speed=10g
|
||||||
|
port set property portlist=0-47 medium-type=cr
|
||||||
|
port set property portlist=48-53 medium-type=cr4
|
||||||
|
port set property portlist=129-130 medium-type=kr
|
||||||
|
port set adver portlist=129-130 speed-10g-kr
|
||||||
|
port set property portlist=129-130 an=enable
|
||||||
|
port set property portlist=129-130 admin=enable
|
||||||
|
port set property portlist=0-53 admin=disable
|
||||||
@ -0,0 +1,404 @@
|
|||||||
|
init start stage low-level
|
||||||
|
init set port-map port=0 eth-macro=2 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=1 eth-macro=2 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=2 eth-macro=2 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=3 eth-macro=2 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=4 eth-macro=3 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=5 eth-macro=3 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=6 eth-macro=3 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=7 eth-macro=3 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=8 eth-macro=4 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=9 eth-macro=4 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=10 eth-macro=4 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=11 eth-macro=4 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=12 eth-macro=5 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=13 eth-macro=5 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=14 eth-macro=5 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=15 eth-macro=5 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=16 eth-macro=8 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=17 eth-macro=8 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=18 eth-macro=8 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=19 eth-macro=8 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=20 eth-macro=10 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=21 eth-macro=10 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=22 eth-macro=10 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=23 eth-macro=10 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=24 eth-macro=12 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=25 eth-macro=12 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=26 eth-macro=12 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=27 eth-macro=12 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=28 eth-macro=14 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=29 eth-macro=14 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=30 eth-macro=14 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=31 eth-macro=14 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=32 eth-macro=16 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=33 eth-macro=16 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=34 eth-macro=16 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=35 eth-macro=16 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=36 eth-macro=17 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=37 eth-macro=17 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=38 eth-macro=17 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=39 eth-macro=17 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=40 eth-macro=18 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=41 eth-macro=18 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=42 eth-macro=18 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=43 eth-macro=18 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=44 eth-macro=19 lane=0 max-speed=25g active=true
|
||||||
|
init set port-map port=45 eth-macro=19 lane=1 max-speed=25g active=true
|
||||||
|
init set port-map port=46 eth-macro=19 lane=2 max-speed=25g active=true
|
||||||
|
init set port-map port=47 eth-macro=19 lane=3 max-speed=25g active=true
|
||||||
|
init set port-map port=48 eth-macro=20 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=49 eth-macro=21 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=50 eth-macro=26 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=51 eth-macro=27 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=52 eth-macro=28 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=53 eth-macro=29 lane=0 max-speed=100g active=true
|
||||||
|
init set port-map port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
|
||||||
|
init set port-map port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
|
||||||
|
init start stage task-rsrc
|
||||||
|
init start stage module
|
||||||
|
init start stage task
|
||||||
|
phy set lane-swap portlist=0 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=1 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=2 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=3 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=4 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=5 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=6 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=7 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=8 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=9 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=10 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=11 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=12 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=13 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=14 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=15 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=16 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=17 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=18 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=19 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=20 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=21 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=22 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=23 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=24 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=25 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=26 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=27 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=28 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=29 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=30 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=31 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=32 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=33 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=34 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=35 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=36 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=37 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=38 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=39 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=40 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=41 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=42 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=43 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=44 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set lane-swap portlist=45 lane-cnt=1 property=tx data=0x1
|
||||||
|
phy set lane-swap portlist=46 lane-cnt=1 property=tx data=0x2
|
||||||
|
phy set lane-swap portlist=47 lane-cnt=1 property=tx data=0x3
|
||||||
|
phy set lane-swap portlist=48-53 lane-cnt=4 property=tx data=0x03.02.01.00
|
||||||
|
phy set lane-swap portlist=0 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=1 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=2 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=3 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=4 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=5 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=6 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=7 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=8 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=9 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=10 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=11 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=12 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=13 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=14 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=15 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=16 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=17 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=18 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=19 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=20 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=21 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=22 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=23 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=24 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=25 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=26 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=27 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=28 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=29 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=30 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=31 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=32 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=33 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=34 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=35 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=36 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=37 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=38 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=39 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=40 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=41 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=42 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=43 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=44 lane-cnt=1 property=rx data=0x1
|
||||||
|
phy set lane-swap portlist=45 lane-cnt=1 property=rx data=0x2
|
||||||
|
phy set lane-swap portlist=46 lane-cnt=1 property=rx data=0x3
|
||||||
|
phy set lane-swap portlist=47 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set lane-swap portlist=48-53 lane-cnt=4 property=rx data=0x03.02.01.00
|
||||||
|
phy set polarity-rev portlist=0 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=1 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=2 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=3 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=4 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=5 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=6 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=7 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=8 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=9 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=10 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=11 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=12 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=13 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=14 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=15 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=16 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=17 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=18 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=19 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=20 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=21 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=22 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=23 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=24 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=25 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=26 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=27 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=28 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=29 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=30 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=31 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=32 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=33 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=34 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=35 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=36 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=37 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=38 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=39 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=40 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=41 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=42 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=43 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=44 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=45 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=46 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=47 lane-cnt=1 property=tx data=0x0
|
||||||
|
phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=0 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=1 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=2 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=3 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=4 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=5 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=6 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=7 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=8 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=9 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=10 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=11 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=12 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=13 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=14 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=15 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=16 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=17 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=18 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=19 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=20 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=21 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=22 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=23 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=24 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=25 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=26 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=27 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=28 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=29 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=30 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=31 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=32 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=33 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=34 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=35 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=36 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=37 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=38 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=39 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=40 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=41 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=42 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=43 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=44 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=45 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=46 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=47 lane-cnt=1 property=rx data=0x0
|
||||||
|
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set polarity-rev portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=cn1 data=0x1.1.1.1
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
|
||||||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=cn1 data=0x1.1.1.1
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
|
||||||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
|
||||||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1C.1C.1C.1C
|
||||||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
|
||||||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
|
||||||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c1 data=0x6.6.6.6
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
|
||||||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1B.1B.1B.1B
|
||||||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=cn1 data=0x0.0.0.0
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
|
||||||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c1 data=0x8.8.8.8
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c2 data=0x2.2.2.2
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=cn1 data=0x1.1.1.1
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1A.1A.1A.1A
|
||||||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c1 data=0x7.7.7.7
|
||||||
|
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=2 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=3 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=4 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=5 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=6 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=7 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=8 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=9 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=10 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=11 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=12 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=13 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=14 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=15 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=16 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=17 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=18 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=19 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=20 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=21 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=22 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=23 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=24 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=25 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=26 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=27 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=28 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=29 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=30 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=31 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=32 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=33 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=34 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=35 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=36 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=37 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=38 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=39 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=40 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=41 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=42 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=43 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=44 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=45 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=46 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=47 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=48 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=49 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=50 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=51 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=52 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=53 devad=0x1E addr=0x2 data=0x8000
|
||||||
|
phy set mdio portlist=129 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
phy set mdio portlist=130 devad=0x1E addr=0x2 data=0x0000
|
||||||
|
port set property portlist=0-47 speed=25g
|
||||||
|
port set property portlist=48-53 speed=100g
|
||||||
|
port set property portlist=129-130 speed=10g
|
||||||
|
port set property portlist=0-47 medium-type=sr
|
||||||
|
port set property portlist=48-53 medium-type=sr4
|
||||||
|
port set property portlist=129-130 medium-type=kr
|
||||||
|
port set adver portlist=129-130 speed-10g-kr
|
||||||
|
port set property portlist=129-130 an=enable
|
||||||
|
port set property portlist=129-130 admin=enable
|
||||||
|
port set property portlist=0-53 admin=disable
|
||||||
@ -1,55 +1,55 @@
|
|||||||
# name lanes alias index
|
# name lanes alias index speed
|
||||||
Ethernet0 8 Ethernet1/1 0
|
Ethernet0 8 Ethernet1/1 0 25000
|
||||||
Ethernet1 9 Ethernet2/1 1
|
Ethernet1 9 Ethernet2/1 1 25000
|
||||||
Ethernet2 10 Ethernet3/1 2
|
Ethernet2 10 Ethernet3/1 2 25000
|
||||||
Ethernet3 11 Ethernet4/1 3
|
Ethernet3 11 Ethernet4/1 3 25000
|
||||||
Ethernet4 12 Ethernet5/1 4
|
Ethernet4 12 Ethernet5/1 4 25000
|
||||||
Ethernet5 13 Ethernet6/1 5
|
Ethernet5 13 Ethernet6/1 5 25000
|
||||||
Ethernet6 14 Ethernet7/1 6
|
Ethernet6 14 Ethernet7/1 6 25000
|
||||||
Ethernet7 15 Ethernet8/1 7
|
Ethernet7 15 Ethernet8/1 7 25000
|
||||||
Ethernet8 16 Ethernet9/1 8
|
Ethernet8 16 Ethernet9/1 8 25000
|
||||||
Ethernet9 17 Ethernet10/1 9
|
Ethernet9 17 Ethernet10/1 9 25000
|
||||||
Ethernet10 18 Ethernet11/1 10
|
Ethernet10 18 Ethernet11/1 10 25000
|
||||||
Ethernet11 19 Ethernet12/1 11
|
Ethernet11 19 Ethernet12/1 11 25000
|
||||||
Ethernet12 20 Ethernet13/1 12
|
Ethernet12 20 Ethernet13/1 12 25000
|
||||||
Ethernet13 21 Ethernet14/1 13
|
Ethernet13 21 Ethernet14/1 13 25000
|
||||||
Ethernet14 22 Ethernet15/1 14
|
Ethernet14 22 Ethernet15/1 14 25000
|
||||||
Ethernet15 23 Ethernet16/1 15
|
Ethernet15 23 Ethernet16/1 15 25000
|
||||||
Ethernet16 32 Ethernet17/1 16
|
Ethernet16 32 Ethernet17/1 16 25000
|
||||||
Ethernet17 33 Ethernet18/1 17
|
Ethernet17 33 Ethernet18/1 17 25000
|
||||||
Ethernet18 34 Ethernet19/1 18
|
Ethernet18 34 Ethernet19/1 18 25000
|
||||||
Ethernet19 35 Ethernet20/1 19
|
Ethernet19 35 Ethernet20/1 19 25000
|
||||||
Ethernet20 40 Ethernet21/1 20
|
Ethernet20 40 Ethernet21/1 20 25000
|
||||||
Ethernet21 41 Ethernet22/1 21
|
Ethernet21 41 Ethernet22/1 21 25000
|
||||||
Ethernet22 42 Ethernet23/1 22
|
Ethernet22 42 Ethernet23/1 22 25000
|
||||||
Ethernet23 43 Ethernet24/1 23
|
Ethernet23 43 Ethernet24/1 23 25000
|
||||||
Ethernet24 48 Ethernet25/1 24
|
Ethernet24 48 Ethernet25/1 24 25000
|
||||||
Ethernet25 49 Ethernet26/1 25
|
Ethernet25 49 Ethernet26/1 25 25000
|
||||||
Ethernet26 50 Ethernet27/1 26
|
Ethernet26 50 Ethernet27/1 26 25000
|
||||||
Ethernet27 51 Ethernet28/1 27
|
Ethernet27 51 Ethernet28/1 27 25000
|
||||||
Ethernet28 56 Ethernet29/1 28
|
Ethernet28 56 Ethernet29/1 28 25000
|
||||||
Ethernet29 57 Ethernet30/1 29
|
Ethernet29 57 Ethernet30/1 29 25000
|
||||||
Ethernet30 58 Ethernet31/1 30
|
Ethernet30 58 Ethernet31/1 30 25000
|
||||||
Ethernet31 59 Ethernet32/1 31
|
Ethernet31 59 Ethernet32/1 31 25000
|
||||||
Ethernet32 64 Ethernet33/1 32
|
Ethernet32 64 Ethernet33/1 32 25000
|
||||||
Ethernet33 65 Ethernet34/1 33
|
Ethernet33 65 Ethernet34/1 33 25000
|
||||||
Ethernet34 66 Ethernet35/1 34
|
Ethernet34 66 Ethernet35/1 34 25000
|
||||||
Ethernet35 67 Ethernet36/1 35
|
Ethernet35 67 Ethernet36/1 35 25000
|
||||||
Ethernet36 68 Ethernet37/1 36
|
Ethernet36 68 Ethernet37/1 36 25000
|
||||||
Ethernet37 69 Ethernet38/1 37
|
Ethernet37 69 Ethernet38/1 37 25000
|
||||||
Ethernet38 70 Ethernet39/1 38
|
Ethernet38 70 Ethernet39/1 38 25000
|
||||||
Ethernet39 71 Ethernet40/1 39
|
Ethernet39 71 Ethernet40/1 39 25000
|
||||||
Ethernet40 72 Ethernet41/1 40
|
Ethernet40 72 Ethernet41/1 40 25000
|
||||||
Ethernet41 73 Ethernet42/1 41
|
Ethernet41 73 Ethernet42/1 41 25000
|
||||||
Ethernet42 74 Ethernet43/1 42
|
Ethernet42 74 Ethernet43/1 42 25000
|
||||||
Ethernet43 75 Ethernet44/1 43
|
Ethernet43 75 Ethernet44/1 43 25000
|
||||||
Ethernet44 76 Ethernet45/1 44
|
Ethernet44 76 Ethernet45/1 44 25000
|
||||||
Ethernet45 77 Ethernet46/1 45
|
Ethernet45 77 Ethernet46/1 45 25000
|
||||||
Ethernet46 78 Ethernet47/1 46
|
Ethernet46 78 Ethernet47/1 46 25000
|
||||||
Ethernet47 79 Ethernet48/1 47
|
Ethernet47 79 Ethernet48/1 47 25000
|
||||||
Ethernet48 84,85,86,87 Ethernet49/1 48
|
Ethernet48 84,85,86,87 Ethernet49/1 48 100000
|
||||||
Ethernet49 80,81,82,83 Ethernet50/1 49
|
Ethernet49 80,81,82,83 Ethernet50/1 49 100000
|
||||||
Ethernet50 104,105,106,107 Ethernet51/1 50
|
Ethernet50 104,105,106,107 Ethernet51/1 50 100000
|
||||||
Ethernet51 108,109,110,111 Ethernet52/1 51
|
Ethernet51 108,109,110,111 Ethernet52/1 51 100000
|
||||||
Ethernet52 112,113,114,115 Ethernet53/1 52
|
Ethernet52 112,113,114,115 Ethernet53/1 52 100000
|
||||||
Ethernet53 116,117,118,119 Ethernet54/1 53
|
Ethernet53 116,117,118,119 Ethernet54/1 53 100000
|
||||||
|
|||||||
@ -410,5 +410,5 @@ port set property portlist=48-53 medium-type=sr4
|
|||||||
port set property portlist=129-130 medium-type=kr
|
port set property portlist=129-130 medium-type=kr
|
||||||
port set adver portlist=129-130 speed-10g-kr
|
port set adver portlist=129-130 speed-10g-kr
|
||||||
port set property portlist=129-130 an=enable
|
port set property portlist=129-130 an=enable
|
||||||
port set property portlist=0-53,129-130 admin=enable
|
port set property unit=0 portlist=129-130 admin=enable
|
||||||
|
port set property unit=0 portlist=0-53 admin=disable
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
SAI_INIT_CONFIG_FILE=/usr/share/sonic/platform/led_proc_init.nps
|
SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/proc_init.nps
|
||||||
SAI_DSH_CONFIG_FILE=/usr/share/sonic/hwsku/port_config.nps
|
SAI_DSH_CONFIG_FILE=/usr/share/sonic/hwsku/port_config.nps
|
||||||
10
device/accton/x86_64-accton_as7116_54x-r0/fancontrol
Normal file
10
device/accton/x86_64-accton_as7116_54x-r0/fancontrol
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
INTERVAL=10
|
||||||
|
FCTEMPS=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/20-004a/hwmon/hwmon*/temp1_input /sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/19-0049/hwmon/hwmon*/temp1_input /sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/17-004b/hwmon/hwmon*/temp1_input
|
||||||
|
FCFANS=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/1-0063/fan1_input /sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/1-0063/fan2_input
|
||||||
|
/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/1-0063/fan3_input /sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/1-0063/fan4_input /sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=/sys/bus/i2c/devices/1-0063/fan5_input
|
||||||
|
MINTEMP=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=49
|
||||||
|
MAXTEMP=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=58
|
||||||
|
MINSTART=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=100
|
||||||
|
MINSTOP=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=40
|
||||||
|
MINPWM=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=40
|
||||||
|
MAXPWM=/sys/bus/i2c/devices/1-0063/fan_duty_cycle_percentage=100
|
||||||
@ -6,6 +6,8 @@ try:
|
|||||||
except ImportError, e:
|
except ImportError, e:
|
||||||
raise ImportError (str(e) + "- required module not found")
|
raise ImportError (str(e) + "- required module not found")
|
||||||
|
|
||||||
|
SFP_STATUS_INSERTED = '1'
|
||||||
|
SFP_STATUS_REMOVED = '0'
|
||||||
|
|
||||||
class SfpUtil(SfpUtilBase):
|
class SfpUtil(SfpUtilBase):
|
||||||
"""Platform specific SfpUtill class"""
|
"""Platform specific SfpUtill class"""
|
||||||
@ -75,17 +77,21 @@ class SfpUtil(SfpUtilBase):
|
|||||||
|
|
||||||
_qsfp_ports = range(_qsfp_port_start, _ports_in_block + 1)
|
_qsfp_ports = range(_qsfp_port_start, _ports_in_block + 1)
|
||||||
|
|
||||||
|
_present_status = dict()
|
||||||
|
|
||||||
def __init__(self):
|
def __init__(self):
|
||||||
eeprom_path = '/sys/bus/i2c/devices/{0}-0050/sfp_eeprom'
|
eeprom_path = '/sys/bus/i2c/devices/{0}-0050/sfp_eeprom'
|
||||||
for x in range(self._port_start, self._port_end + 1):
|
for x in range(self._port_start, self._port_end + 1):
|
||||||
port_eeprom_path = eeprom_path.format(self._port_to_i2c_mapping[x])
|
port_eeprom_path = eeprom_path.format(self._port_to_i2c_mapping[x])
|
||||||
self._port_to_eeprom_mapping[x] = port_eeprom_path
|
self._port_to_eeprom_mapping[x] = port_eeprom_path
|
||||||
|
self._present_status[x] = SFP_STATUS_REMOVED
|
||||||
|
|
||||||
SfpUtilBase.__init__(self)
|
SfpUtilBase.__init__(self)
|
||||||
|
|
||||||
def reset(self, port_num):
|
def reset(self, port_num):
|
||||||
# Check for invalid port_num
|
# Check for invalid port_num
|
||||||
if port_num < self._port_start or port_num > self._port_end:
|
if port_num < self._qsfp_port_start or port_num > self._port_end:
|
||||||
|
print "Error: port %d is not qsfp port" % port_num
|
||||||
return False
|
return False
|
||||||
|
|
||||||
path = "/sys/bus/i2c/devices/{0}-0050/sfp_port_reset"
|
path = "/sys/bus/i2c/devices/{0}-0050/sfp_port_reset"
|
||||||
@ -151,3 +157,15 @@ class SfpUtil(SfpUtilBase):
|
|||||||
@property
|
@property
|
||||||
def port_to_eeprom_mapping(self):
|
def port_to_eeprom_mapping(self):
|
||||||
return self._port_to_eeprom_mapping
|
return self._port_to_eeprom_mapping
|
||||||
|
|
||||||
|
def get_transceiver_change_event(self, timeout=0):
|
||||||
|
ret_present = dict()
|
||||||
|
for phy_port in range(self._port_start, self._port_end + 1):
|
||||||
|
last_present_status = SFP_STATUS_INSERTED if self.get_presence(phy_port) else SFP_STATUS_REMOVED
|
||||||
|
if self._present_status[phy_port] != last_present_status:
|
||||||
|
ret_present[phy_port] = last_present_status
|
||||||
|
self._present_status[phy_port] = last_present_status
|
||||||
|
|
||||||
|
time.sleep(2)
|
||||||
|
|
||||||
|
return True, ret_present
|
||||||
@ -1,6 +1,5 @@
|
|||||||
sonic-accton-platform-modules (1.0.0) unstable; urgency=low
|
sonic-accton-platform-modules (1.0.1) unstable; urgency=low
|
||||||
|
|
||||||
* Add support for AS7116-54X series
|
* Add support for AS7116-54X series
|
||||||
|
|
||||||
-- developer <developer@nephos.com> Wed, 29 Mar 2017 11:00:00 +0800
|
-- developer <developer@nephos.com> Wed, 29 Mar 2017 11:00:00 +0800
|
||||||
|
|
||||||
|
|||||||
@ -59,9 +59,9 @@ binary-indep:
|
|||||||
|
|
||||||
# Custom package commands
|
# Custom package commands
|
||||||
(for mod in $(MODULE_DIRS); do \
|
(for mod in $(MODULE_DIRS); do \
|
||||||
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
|
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
|
||||||
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod}/usr/local/bin; \
|
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /usr/local/bin; \
|
||||||
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod}/lib/systemd/system; \
|
dh_installdirs -p$(PACKAGE_PRE_NAME)-$${mod} /lib/systemd/system; \
|
||||||
cp $(MOD_SRC_DIR)/$${mod}/$(MODULE_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
|
cp $(MOD_SRC_DIR)/$${mod}/$(MODULE_DIR)/*.ko debian/$(PACKAGE_PRE_NAME)-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \
|
||||||
cp $(MOD_SRC_DIR)/$${mod}/$(UTILS_DIR)/* debian/$(PACKAGE_PRE_NAME)-$${mod}/usr/local/bin/; \
|
cp $(MOD_SRC_DIR)/$${mod}/$(UTILS_DIR)/* debian/$(PACKAGE_PRE_NAME)-$${mod}/usr/local/bin/; \
|
||||||
cp $(MOD_SRC_DIR)/$${mod}/$(SERVICE_DIR)/*.service debian/$(PACKAGE_PRE_NAME)-$${mod}/lib/systemd/system/; \
|
cp $(MOD_SRC_DIR)/$${mod}/$(SERVICE_DIR)/*.service debian/$(PACKAGE_PRE_NAME)-$${mod}/lib/systemd/system/; \
|
||||||
|
|||||||
Reference in New Issue
Block a user