[device/celestica]: Add xcvrd event support for Seastone-DX010 (#5896)
- Add sysfs interrupt to notify userspace app of external interrupt - Implement get_change_event() in chassis api.
This commit is contained in:
Wirut Getbamrung
GitHub
parent
9580b0407f
commit
4257c792a2
@ -9,6 +9,9 @@
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try:
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import sys
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from sonic_platform_base.chassis_base import ChassisBase
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from sonic_platform_base.sonic_sfp.sfputilhelper import SfpUtilHelper
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from sonic_py_common import device_info
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from .event import SfpEvent
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from .helper import APIHelper
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except ImportError as e:
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raise ImportError(str(e) + "- required module not found")
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@ -45,9 +48,14 @@ class Chassis(ChassisBase):
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self.__initialize_components()
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def __initialize_sfp(self):
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sfputil_helper = SfpUtilHelper()
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port_config_file_path = device_info.get_path_to_port_config_file()
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sfputil_helper.read_porttab_mappings(port_config_file_path, 0)
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from sonic_platform.sfp import Sfp
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for index in range(0, NUM_SFP):
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sfp = Sfp(index)
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name_idx = 0 if index+1 == NUM_SFP else index+1
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sfp = Sfp(index, sfputil_helper.logical[name_idx])
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self._sfp_list.append(sfp)
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self.sfp_module_initialized = True
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@ -141,6 +149,38 @@ class Chassis(ChassisBase):
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return prev_reboot_cause
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def get_change_event(self, timeout=0):
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"""
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Returns a nested dictionary containing all devices which have
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experienced a change at chassis level
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Args:
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timeout: Timeout in milliseconds (optional). If timeout == 0,
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this method will block until a change is detected.
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Returns:
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(bool, dict):
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- True if call successful, False if not;
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- A nested dictionary where key is a device type,
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value is a dictionary with key:value pairs in the format of
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{'device_id':'device_event'},
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where device_id is the device ID for this device and
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device_event,
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status='1' represents device inserted,
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status='0' represents device removed.
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Ex. {'fan':{'0':'0', '2':'1'}, 'sfp':{'11':'0'}}
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indicates that fan 0 has been removed, fan 2
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has been inserted and sfp 11 has been removed.
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"""
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# SFP event
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if not self.sfp_module_initialized:
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self.__initialize_sfp()
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sfp_event = SfpEvent(self._sfp_list).get_sfp_event(timeout)
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if sfp_event:
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return True, {'sfp': sfp_event}
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return False, {'sfp': {}}
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##############################################################
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######################## SFP methods #########################
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##############################################################
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@ -0,0 +1,52 @@
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try:
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import select
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from .helper import APIHelper
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from sonic_py_common.logger import Logger
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except ImportError as e:
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raise ImportError(repr(e) + " - required module not found")
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class SfpEvent:
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''' Listen to insert/remove sfp events '''
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QSFP_MODPRS_IRQ = '/sys/devices/platform/dx010_cpld/qsfp_modprs_irq'
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GPIO_SUS6 = "/sys/devices/platform/slx-ich.0/sci_int_gpio_sus6"
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def __init__(self, sfp_list):
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self._api_helper = APIHelper()
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self._sfp_list = sfp_list
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self._logger = Logger()
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def get_sfp_event(self, timeout):
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epoll = select.epoll()
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port_dict = {}
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timeout_sec = timeout/1000
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try:
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# We get notified when there is an SCI interrupt from GPIO SUS6
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fd = open(self.GPIO_SUS6, "r")
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fd.read()
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epoll.register(fd.fileno(), select.EPOLLIN & select.EPOLLET)
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events = epoll.poll(timeout=timeout_sec if timeout != 0 else -1)
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if events:
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# Read the QSFP ABS interrupt & status registers
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port_changes = self._api_helper.read_one_line_file(
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self.QSFP_MODPRS_IRQ)
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changes = int(port_changes, 16)
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for sfp in self._sfp_list:
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change = (changes >> sfp.port_num-1) & 1
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if change == 1:
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port_dict[str(sfp.port_num)] = str(
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int(sfp.get_presence()))
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return port_dict
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except Exception as e:
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self._logger.log_error("Failed to detect SfpEvent - " + repr(e))
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return False
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finally:
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fd.close()
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epoll.close()
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return False
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@ -17,7 +17,6 @@ try:
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from sonic_platform_base.sonic_sfp.sff8436 import sff8436InterfaceId
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from sonic_platform_base.sonic_sfp.sff8436 import sff8436Dom
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from sonic_platform_base.sonic_sfp.inf8628 import inf8628InterfaceId
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from sonic_platform_base.sonic_sfp.sfputilhelper import SfpUtilHelper
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from .helper import APIHelper
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except ImportError as e:
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raise ImportError(str(e) + "- required module not found")
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@ -166,10 +165,8 @@ class Sfp(SfpBase):
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RESET_PATH = "/sys/devices/platform/dx010_cpld/qsfp_reset"
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LP_PATH = "/sys/devices/platform/dx010_cpld/qsfp_lpmode"
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PRS_PATH = "/sys/devices/platform/dx010_cpld/qsfp_modprs"
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PLATFORM_ROOT_PATH = "/usr/share/sonic/device"
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PMON_HWSKU_PATH = "/usr/share/sonic/hwsku"
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def __init__(self, sfp_index):
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def __init__(self, sfp_index, sfp_name):
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SfpBase.__init__(self)
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# Init index
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self.index = sfp_index
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@ -177,8 +174,7 @@ class Sfp(SfpBase):
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self.dom_supported = False
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self.sfp_type, self.port_name = self.__get_sfp_info()
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self._api_helper = APIHelper()
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self.platform = self._api_helper.platform
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self.hwsku = self._api_helper.hwsku
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self.name = sfp_name
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# Init eeprom path
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eeprom_path = '/sys/bus/i2c/devices/i2c-{0}/{0}-0050/eeprom'
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@ -233,12 +229,6 @@ class Sfp(SfpBase):
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else:
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return 'N/A'
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def __get_path_to_port_config_file(self):
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platform_path = "/".join([self.PLATFORM_ROOT_PATH, self.platform])
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hwsku_path = "/".join([platform_path, self.hwsku]
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) if self._api_helper.is_host() else self.PMON_HWSKU_PATH
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return "/".join([hwsku_path, "port_config.ini"])
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def __read_eeprom_specific_bytes(self, offset, num_bytes):
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sysfsfile_eeprom = None
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eeprom_raw = []
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@ -1317,11 +1307,7 @@ class Sfp(SfpBase):
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Returns:
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string: The name of the device
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"""
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sfputil_helper = SfpUtilHelper()
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sfputil_helper.read_porttab_mappings(
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self.__get_path_to_port_config_file())
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name = sfputil_helper.logical[self.index] or "Unknown"
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return name
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return self.name
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def get_presence(self):
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"""
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@ -46,6 +46,7 @@ start)
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modprobe dx010_wdt
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modprobe leds-dx010
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modprobe lm75
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modprobe slx_gpio_ich
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found=0
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for devnum in 0 1; do
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@ -1 +1 @@
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obj-m := dx010_cpld.o mc24lc64t.o emc2305.o dx010_wdt.o leds-dx010.o
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obj-m := dx010_cpld.o mc24lc64t.o emc2305.o dx010_wdt.o leds-dx010.o slx_gpio_ich.o
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@ -65,6 +65,22 @@
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#define INT2229 0x3d6
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#define INT3032 0x3d7
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#define ABS_INT0108 0x260
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#define ABS_INT0910 0x261
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#define ABS_INT1118 0x2E0
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#define ABS_INT1921 0x2E1
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#define ABS_INT2229 0x3E0
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#define ABS_INT3032 0x3E1
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#define ABS_INT_MSK0108 0x262
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#define ABS_INT_MSK0910 0x263
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#define ABS_INT_MSK1118 0x2E2
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#define ABS_INT_MSK1921 0x2E3
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#define ABS_INT_MSK2229 0x3E2
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#define ABS_INT_MSK3032 0x3E3
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#define CPLD4_INT0 0x313
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#define CPLD4_INT0_MSK 0x315
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#define LENGTH_PORT_CPLD 34
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#define PORT_BANK1_START 1
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@ -76,52 +92,42 @@
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#define PORT_SFPP1 33
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#define PORT_SFPP2 34
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#define PORT_ID_BANK1 0x210
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#define PORT_ID_BANK2 0x290
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#define PORT_ID_BANK3 0x390
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#define CPLD_I2C_CLK_100Khz_BIT BIT(6)
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#define CPLD_I2C_DATA_SZ_MASK GENMASK(7,4)
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#define CPLD_I2C_CMD_SZ_MASK GENMASK(1,0)
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#define CPLD_I2C_ERR BIT(7)
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#define CPLD_I2C_BUSY BIT(6)
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#define CPLD_I2C_RST_BIT BIT(0)
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#define CPLD_I2C_RESET 0
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#define CPLD_I2C_UNRESET 1
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#define CPLD_I2C_DATA_SZ_MAX 8
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#define CPLD_I2C_CMD_SZ_MAX 3
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#define OPCODE_ID_BANK1 0x211
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#define OPCODE_ID_BANK2 0x291
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#define OPCODE_ID_BANK3 0x391
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#define DEVADDR_ID_BANK1 0x212
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#define DEVADDR_ID_BANK2 0x292
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#define DEVADDR_ID_BANK3 0x392
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#define CPLD_I2C_BANK1_BASE 0x210
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#define CPLD_I2C_BANK2_BASE 0x290
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#define CPLD_I2C_BANK3_BASE 0x390
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#define CMDBYT_ID_BANK1 0x213
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#define CMDBYT_ID_BANK2 0x293
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#define CMDBYT_ID_BANK3 0x393
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#define I2C_PORT_ID 0x0
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#define I2C_OPCODE 0x1
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#define I2C_DEV_ADDR 0x2
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#define I2C_CMD_BYT0 0x3
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#define I2C_SSR 0x6
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#define I2C_WRITE_DATA 0x10
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#define I2C_READ_DATA 0x20
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#define WRITE_ID_BANK1 0x220
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#define WRITE_ID_BANK2 0x2A0
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#define WRITE_ID_BANK3 0x3A0
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/*
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* private data to send to I2C core
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*/
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struct current_xfer {
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u8 addr;
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u8 cmd[CPLD_I2C_CMD_SZ_MAX];
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u8 cmd_len;
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u8 data_len;
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union i2c_smbus_data *data;
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};
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#define READ_ID_BANK1 0x230
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#define READ_ID_BANK2 0x2B0
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#define READ_ID_BANK3 0x3B0
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#define SSRR_ID_BANK1 0x216
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#define SSRR_ID_BANK2 0x296
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#define SSRR_ID_BANK3 0x396
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#define HST_CNTL2_QUICK 0x00
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#define HST_CNTL2_BYTE 0x01
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#define HST_CNTL2_BYTE_DATA 0x02
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#define HST_CNTL2_WORD_DATA 0x03
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#define HST_CNTL2_BLOCK 0x05
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/*
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* private data of I2C adapter
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* base_addr: Base address of this I2C adapter core.
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* port_id: The port ID, use to mux an i2c core to a font panel port.
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* current_xfer: The struct carry current data setup of current smbus transfer.
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*/
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struct dx010_i2c_data {
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int base_addr;
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int portid;
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struct current_xfer curr_xfer;
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};
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struct dx010_cpld_data {
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@ -332,12 +338,136 @@ static ssize_t get_modirq(struct device *dev, struct device_attribute *devattr,
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return sprintf(buf,"0x%8.8lx\n", irq & 0xffffffff);
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}
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static ssize_t get_modprs_irq(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long prs_int = 0;
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mutex_lock(&cpld_data->cpld_lock);
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/* Clear interrupt source */
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inb(CPLD4_INT0);
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prs_int =
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(inb(ABS_INT3032) & 0x07) << (24+5) |
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inb(ABS_INT2229) << (24-3) |
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(inb(ABS_INT1921) & 0x07) << (16 + 2) |
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inb(ABS_INT1118) << (16-6) |
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(inb(ABS_INT0910) & 0x03 ) << 8 |
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inb(ABS_INT0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", prs_int & 0xffffffff);
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}
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static ssize_t get_modprs_msk(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long prs_int_msk = 0;
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mutex_lock(&cpld_data->cpld_lock);
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prs_int_msk =
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(inb(ABS_INT_MSK3032) & 0x07) << (24+5) |
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inb(ABS_INT_MSK2229) << (24-3) |
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(inb(ABS_INT_MSK1921) & 0x07) << (16 + 2) |
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inb(ABS_INT_MSK1118) << (16-6) |
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(inb(ABS_INT_MSK0910) & 0x03 ) << 8 |
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inb(ABS_INT_MSK0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", prs_int_msk & 0xffffffff);
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}
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static ssize_t set_modprs_msk(struct device *dev, struct device_attribute *devattr,
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const char *buf, size_t count)
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{
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unsigned long prs_int_msk;
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int err;
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mutex_lock(&cpld_data->cpld_lock);
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err = kstrtoul(buf, 16, &prs_int_msk);
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if (err)
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{
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mutex_unlock(&cpld_data->cpld_lock);
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return err;
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}
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outb( (prs_int_msk >> 0) & 0xFF, ABS_INT_MSK0108);
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outb( (prs_int_msk >> 8) & 0x03, ABS_INT_MSK0910);
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outb( (prs_int_msk >> 10) & 0xFF, ABS_INT_MSK1118);
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outb( (prs_int_msk >> 18) & 0x07, ABS_INT_MSK1921);
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outb( (prs_int_msk >> 21) & 0xFF, ABS_INT_MSK2229);
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outb( (prs_int_msk >> 29) & 0x07, ABS_INT_MSK3032);
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mutex_unlock(&cpld_data->cpld_lock);
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return count;
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}
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static ssize_t get_cpld4_int0(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned char int0 = 0;
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mutex_lock(&cpld_data->cpld_lock);
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int0 = inb(CPLD4_INT0);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%2.2x\n", int0 & 0xff);
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}
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static ssize_t get_cpld4_int0_msk(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned char int0_msk = 0;
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mutex_lock(&cpld_data->cpld_lock);
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int0_msk = inb(CPLD4_INT0_MSK);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%2.2x\n", int0_msk & 0xff);
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}
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static ssize_t set_cpld4_int0_msk(struct device *dev, struct device_attribute *devattr,
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const char *buf, size_t count)
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{
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unsigned long int0_msk;
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int err;
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mutex_lock(&cpld_data->cpld_lock);
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err = kstrtoul(buf, 16, &int0_msk);
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if (err)
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{
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mutex_unlock(&cpld_data->cpld_lock);
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return err;
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}
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outb(int0_msk & 0x3f, CPLD4_INT0_MSK);
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mutex_unlock(&cpld_data->cpld_lock);
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return count;
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}
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static DEVICE_ATTR_RW(getreg);
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static DEVICE_ATTR_WO(setreg);
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static DEVICE_ATTR(qsfp_reset, S_IRUGO | S_IWUSR, get_reset, set_reset);
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static DEVICE_ATTR(qsfp_lpmode, S_IRUGO | S_IWUSR, get_lpmode, set_lpmode);
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static DEVICE_ATTR(qsfp_modprs, S_IRUGO, get_modprs, NULL);
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static DEVICE_ATTR(qsfp_modirq, S_IRUGO, get_modirq, NULL);
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static DEVICE_ATTR(qsfp_modprs_irq, S_IRUGO, get_modprs_irq, NULL);
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static DEVICE_ATTR(qsfp_modprs_msk, S_IRUGO | S_IWUSR, get_modprs_msk, set_modprs_msk);
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static DEVICE_ATTR(cpld4_int0, S_IRUGO, get_cpld4_int0, NULL);
|
||||
static DEVICE_ATTR(cpld4_int0_msk, S_IRUGO | S_IWUSR, get_cpld4_int0_msk, set_cpld4_int0_msk);
|
||||
|
||||
static struct attribute *dx010_lpc_attrs[] = {
|
||||
&dev_attr_getreg.attr,
|
||||
@ -346,6 +476,10 @@ static struct attribute *dx010_lpc_attrs[] = {
|
||||
&dev_attr_qsfp_lpmode.attr,
|
||||
&dev_attr_qsfp_modprs.attr,
|
||||
&dev_attr_qsfp_modirq.attr,
|
||||
&dev_attr_qsfp_modprs_irq.attr,
|
||||
&dev_attr_qsfp_modprs_msk.attr,
|
||||
&dev_attr_cpld4_int0.attr,
|
||||
&dev_attr_cpld4_int0_msk.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
@ -374,210 +508,179 @@ static struct platform_device cel_dx010_lpc_dev = {
|
||||
}
|
||||
};
|
||||
|
||||
// TODO: Refactoring this function with helper functions.
|
||||
static s32 cpld_smbus_transfer(struct dx010_i2c_data *priv) {
|
||||
|
||||
u8 val;
|
||||
s32 error;
|
||||
unsigned long ioBase;
|
||||
short portid, opcode, devaddr, cmdbyte0, ssr, writedata, readdata;
|
||||
union i2c_smbus_data *data;
|
||||
/**
|
||||
* Read eeprom of QSFP device.
|
||||
* @param a i2c adapter.
|
||||
* @param addr address to read.
|
||||
* @param new_data QSFP port number struct.
|
||||
* @param cmd i2c command.
|
||||
* @return 0 if not error, else the error code.
|
||||
*/
|
||||
static int i2c_read_eeprom(struct i2c_adapter *a, u16 addr,
|
||||
struct dx010_i2c_data *new_data, u8 cmd, union i2c_smbus_data *data){
|
||||
|
||||
error = -EIO;
|
||||
u32 reg;
|
||||
int ioBase=0;
|
||||
char byte;
|
||||
short temp;
|
||||
short portid, opcode, devaddr, cmdbyte0, ssrr, writedata, readdata;
|
||||
__u16 word_data;
|
||||
int error = -EIO;
|
||||
|
||||
mutex_lock(&cpld_data->cpld_lock);
|
||||
|
||||
ioBase = priv->base_addr;
|
||||
data = priv->curr_xfer.data;
|
||||
if (((new_data->portid >= PORT_BANK1_START)
|
||||
&& (new_data->portid <= PORT_BANK1_END))
|
||||
|| (new_data->portid == PORT_SFPP1)
|
||||
|| (new_data->portid == PORT_SFPP2))
|
||||
{
|
||||
portid = PORT_ID_BANK1;
|
||||
opcode = OPCODE_ID_BANK1;
|
||||
devaddr = DEVADDR_ID_BANK1;
|
||||
cmdbyte0 = CMDBYT_ID_BANK1;
|
||||
ssrr = SSRR_ID_BANK1;
|
||||
writedata = WRITE_ID_BANK1;
|
||||
readdata = READ_ID_BANK1;
|
||||
}else if ((new_data->portid >= PORT_BANK2_START) && (new_data->portid <= PORT_BANK2_END)){
|
||||
portid = PORT_ID_BANK2;
|
||||
opcode = OPCODE_ID_BANK2;
|
||||
devaddr = DEVADDR_ID_BANK2;
|
||||
cmdbyte0 = CMDBYT_ID_BANK2;
|
||||
ssrr = SSRR_ID_BANK2;
|
||||
writedata = WRITE_ID_BANK2;
|
||||
readdata = READ_ID_BANK2;
|
||||
}else if ((new_data->portid >= PORT_BANK3_START) && (new_data->portid <= PORT_BANK3_END)){
|
||||
portid = PORT_ID_BANK3;
|
||||
opcode = OPCODE_ID_BANK3;
|
||||
devaddr = DEVADDR_ID_BANK3;
|
||||
cmdbyte0 = CMDBYT_ID_BANK3;
|
||||
ssrr = SSRR_ID_BANK3;
|
||||
writedata = WRITE_ID_BANK3;
|
||||
readdata = READ_ID_BANK3;
|
||||
}else{
|
||||
/* Invalid parameter! */
|
||||
error = -EINVAL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
portid = ioBase + I2C_PORT_ID;
|
||||
opcode = ioBase + I2C_OPCODE;
|
||||
devaddr = ioBase + I2C_DEV_ADDR;
|
||||
cmdbyte0 = ioBase + I2C_CMD_BYT0;
|
||||
ssr = ioBase + I2C_SSR;
|
||||
writedata = ioBase + I2C_WRITE_DATA;
|
||||
readdata = ioBase + I2C_READ_DATA;
|
||||
|
||||
/* Wait for the core to be free */
|
||||
pr_debug("CPLD_I2C Wait busy bit(6) to be cleared\n");
|
||||
do {
|
||||
val = inb(ssr);
|
||||
if ((val & CPLD_I2C_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
} while (true); // Risky - add timeout
|
||||
|
||||
/*
|
||||
* If any error happen here, we do soft-reset
|
||||
* and check the BUSY/ERROR again.
|
||||
*/
|
||||
pr_debug("CPLD_I2C Check error bit(7)\n");
|
||||
if (val & CPLD_I2C_ERR) {
|
||||
pr_debug("CPLD_I2C Error, try soft-reset\n");
|
||||
outb(CPLD_I2C_RESET, ssr);
|
||||
while ((inb(ioBase + ssrr) & 0x40));
|
||||
if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
|
||||
error = -EIO;
|
||||
/* Read error reset the port */
|
||||
outb(0x00, ioBase + ssrr);
|
||||
udelay(3000);
|
||||
outb(CPLD_I2C_UNRESET, ssr);
|
||||
|
||||
val = inb(ssr);
|
||||
if (val & (CPLD_I2C_BUSY | CPLD_I2C_ERR)) {
|
||||
pr_debug("CPLD_I2C Error, core busy after reset\n");
|
||||
error = -EIO;
|
||||
goto exit_unlock;
|
||||
}
|
||||
outb(0x01, ioBase + ssrr);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* Configure PortID */
|
||||
val = priv->portid | CPLD_I2C_CLK_100Khz_BIT;
|
||||
outb(val, portid);
|
||||
pr_debug("CPLD_I2C Write PortID 0x%x\n", val);
|
||||
|
||||
/* Configure OP_Code */
|
||||
val = (priv->curr_xfer.data_len << 4) & CPLD_I2C_DATA_SZ_MASK;
|
||||
val |= (priv->curr_xfer.cmd_len & CPLD_I2C_CMD_SZ_MASK);
|
||||
outb(val, opcode);
|
||||
pr_debug("CPLD_I2C Write OP_Code 0x%x\n", val);
|
||||
|
||||
/* Configure CMD_Byte */
|
||||
outb(priv->curr_xfer.cmd[0], cmdbyte0);
|
||||
pr_debug("CPLD_I2C Write CMD_Byte 0x%x\n", priv->curr_xfer.cmd[0]);
|
||||
|
||||
/* Configure write data buffer */
|
||||
if ((priv->curr_xfer.addr & BIT(0)) == I2C_SMBUS_WRITE){
|
||||
pr_debug("CPLD_I2C Write WR_DATA buffer\n");
|
||||
switch(priv->curr_xfer.data_len){
|
||||
case 1:
|
||||
outb(data->byte, writedata);
|
||||
break;
|
||||
case 2:
|
||||
outb(data->block[0], writedata);
|
||||
outb(data->block[1], ++writedata);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Start transfer, write the device address register */
|
||||
pr_debug("CPLD_I2C Write DEV_ADDR 0x%x\n", priv->curr_xfer.addr);
|
||||
outb(priv->curr_xfer.addr, devaddr);
|
||||
|
||||
/* Wait for transfer finish */
|
||||
pr_debug("CPLD_I2C Wait busy bit(6) to be cleared\n");
|
||||
do {
|
||||
val = inb(ssr);
|
||||
if ((val & CPLD_I2C_BUSY) == 0)
|
||||
break;
|
||||
byte = 0x40 +new_data->portid;
|
||||
reg = cmd;
|
||||
outb(byte, ioBase + portid);
|
||||
outb(reg,ioBase + cmdbyte0);
|
||||
byte = 33;
|
||||
outb(byte, ioBase + opcode);
|
||||
addr = addr << 1;
|
||||
addr |= 0x01;
|
||||
outb(addr, ioBase + devaddr);
|
||||
while ((inb(ioBase + ssrr) & 0x40))
|
||||
{
|
||||
udelay(100);
|
||||
} while (true); // Risky - add timeout
|
||||
}
|
||||
|
||||
pr_debug("CPLD_I2C Check error bit(7)\n");
|
||||
if (val & CPLD_I2C_ERR) {
|
||||
if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
|
||||
/* Read error reset the port */
|
||||
error = -EIO;
|
||||
goto exit_unlock;
|
||||
outb(0x00, ioBase + ssrr);
|
||||
udelay(3000);
|
||||
outb(0x01, ioBase + ssrr);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* Get the data from buffer */
|
||||
if ((priv->curr_xfer.addr & BIT(0)) == I2C_SMBUS_READ){
|
||||
pr_debug("CPLD_I2C Read RD_DATA buffer\n");
|
||||
switch (priv->curr_xfer.data_len) {
|
||||
case 1:
|
||||
data->byte = inb(readdata);
|
||||
break;
|
||||
case 2:
|
||||
data->block[0] = inb(readdata);
|
||||
data->block[1] = inb(++readdata);
|
||||
break;
|
||||
}
|
||||
}
|
||||
temp = ioBase + readdata;
|
||||
word_data = inb(temp);
|
||||
word_data |= (inb(++temp) << 8);
|
||||
|
||||
error = 0;
|
||||
mutex_unlock(&cpld_data->cpld_lock);
|
||||
data->word = word_data;
|
||||
return 0;
|
||||
|
||||
exit_unlock:
|
||||
pr_debug("CPLD_I2C Exit with %d\n", error);
|
||||
exit:
|
||||
mutex_unlock(&cpld_data->cpld_lock);
|
||||
return error;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* dx010_smbus_xfer - execute LPC-SMBus transfer
|
||||
* Returns a negative errno code else zero on success.
|
||||
*/
|
||||
static s32 dx010_smbus_xfer(struct i2c_adapter *adap, u16 addr,
|
||||
unsigned short flags, char read_write,
|
||||
u8 command, int size, union i2c_smbus_data *data) {
|
||||
static int dx010_i2c_access(struct i2c_adapter *a, u16 addr,
|
||||
unsigned short flags, char rw, u8 cmd,
|
||||
int size, union i2c_smbus_data *data)
|
||||
{
|
||||
|
||||
int error = 0;
|
||||
struct dx010_i2c_data *priv;
|
||||
|
||||
priv = i2c_get_adapdata(adap);
|
||||
struct dx010_i2c_data *new_data;
|
||||
|
||||
pr_debug("smbus_xfer called RW:%x CMD:%x SIZE:0x%x",
|
||||
read_write, command, size);
|
||||
|
||||
priv->curr_xfer.addr = (addr << 1) | read_write;
|
||||
priv->curr_xfer.data = data;
|
||||
/* Write the command register */
|
||||
new_data = i2c_get_adapdata(a);
|
||||
|
||||
/* Map the size to what the chip understands */
|
||||
switch (size) {
|
||||
case I2C_SMBUS_QUICK:
|
||||
size = HST_CNTL2_QUICK;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE:
|
||||
priv->curr_xfer.cmd_len = 0;
|
||||
priv->curr_xfer.data_len = 1;
|
||||
size = HST_CNTL2_BYTE;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE_DATA:
|
||||
priv->curr_xfer.cmd_len = 1;
|
||||
priv->curr_xfer.data_len = 1;
|
||||
priv->curr_xfer.cmd[0] = command;
|
||||
size = HST_CNTL2_BYTE_DATA;
|
||||
break;
|
||||
case I2C_SMBUS_WORD_DATA:
|
||||
priv->curr_xfer.cmd_len = 1;
|
||||
priv->curr_xfer.data_len = 2;
|
||||
priv->curr_xfer.cmd[0] = command;
|
||||
size = HST_CNTL2_WORD_DATA;
|
||||
break;
|
||||
case I2C_SMBUS_BLOCK_DATA:
|
||||
size = HST_CNTL2_BLOCK;
|
||||
break;
|
||||
default:
|
||||
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
|
||||
dev_warn(&a->dev, "Unsupported transaction %d\n", size);
|
||||
error = -EOPNOTSUPP;
|
||||
goto Done;
|
||||
}
|
||||
|
||||
error = cpld_smbus_transfer(priv);
|
||||
switch (size) {
|
||||
case HST_CNTL2_BYTE: /* Result put in SMBHSTDAT0 */
|
||||
break;
|
||||
case HST_CNTL2_BYTE_DATA:
|
||||
break;
|
||||
case HST_CNTL2_WORD_DATA:
|
||||
if( 0 == i2c_read_eeprom(a,addr,new_data,cmd,data)){
|
||||
error = 0;
|
||||
}else{
|
||||
error = -EIO;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
Done:
|
||||
return error;
|
||||
}
|
||||
|
||||
// TODO: Add support for I2C_FUNC_SMBUS_PROC_CALL and I2C_FUNC_SMBUS_I2C_BLOCK
|
||||
static u32 dx010_i2c_func(struct i2c_adapter *a) {
|
||||
return I2C_FUNC_SMBUS_READ_BYTE |
|
||||
I2C_FUNC_SMBUS_BYTE_DATA |
|
||||
I2C_FUNC_SMBUS_WORD_DATA;
|
||||
static u32 dx010_i2c_func(struct i2c_adapter *a)
|
||||
{
|
||||
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
||||
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
||||
I2C_FUNC_SMBUS_BLOCK_DATA;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm dx010_i2c_algorithm = {
|
||||
.smbus_xfer = dx010_smbus_xfer,
|
||||
.smbus_xfer = dx010_i2c_access,
|
||||
.functionality = dx010_i2c_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter * cel_dx010_i2c_init(struct platform_device *pdev, int portid)
|
||||
{
|
||||
int error;
|
||||
int base_addr;
|
||||
struct i2c_adapter *new_adapter;
|
||||
struct dx010_i2c_data *priv;
|
||||
|
||||
switch (portid) {
|
||||
case PORT_SFPP1 ... PORT_SFPP2:
|
||||
case PORT_BANK1_START ... PORT_BANK1_END:
|
||||
base_addr = CPLD_I2C_BANK1_BASE;
|
||||
break;
|
||||
case PORT_BANK2_START ... PORT_BANK2_END:
|
||||
base_addr = CPLD_I2C_BANK2_BASE;
|
||||
break;
|
||||
case PORT_BANK3_START ... PORT_BANK3_END:
|
||||
base_addr = CPLD_I2C_BANK3_BASE;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Invalid port adapter ID: %d\n", portid);
|
||||
goto error_exit;
|
||||
}
|
||||
struct i2c_adapter *new_adapter;
|
||||
struct dx010_i2c_data *new_data;
|
||||
|
||||
new_adapter = kzalloc(sizeof(*new_adapter), GFP_KERNEL);
|
||||
if (!new_adapter)
|
||||
@ -585,33 +688,25 @@ static struct i2c_adapter *cel_dx010_i2c_init(struct platform_device *pdev, int
|
||||
|
||||
new_adapter->dev.parent = &pdev->dev;
|
||||
new_adapter->owner = THIS_MODULE;
|
||||
new_adapter->class = I2C_CLASS_DEPRECATED;
|
||||
new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
new_adapter->algo = &dx010_i2c_algorithm;
|
||||
|
||||
snprintf(new_adapter->name, sizeof(new_adapter->name),
|
||||
"SMBus dx010 i2c Adapter port %d", portid);
|
||||
"SMBus dx010 i2c Adapter portid@%04x", portid);
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
goto free_adap;
|
||||
}
|
||||
new_data = kzalloc(sizeof(*new_data), GFP_KERNEL);
|
||||
if (!new_data)
|
||||
return NULL;
|
||||
|
||||
priv->portid = portid;
|
||||
priv->base_addr = base_addr;
|
||||
new_data->portid = portid;
|
||||
|
||||
i2c_set_adapdata(new_adapter,new_data);
|
||||
|
||||
i2c_set_adapdata(new_adapter, priv);
|
||||
error = i2c_add_adapter(new_adapter);
|
||||
if(error)
|
||||
goto free_data;
|
||||
return NULL;
|
||||
|
||||
return new_adapter;
|
||||
|
||||
free_adap:
|
||||
kzfree(new_adapter);
|
||||
free_data:
|
||||
kzfree(priv);
|
||||
error_exit:
|
||||
return NULL;
|
||||
};
|
||||
|
||||
static int cel_dx010_lpc_drv_probe(struct platform_device *pdev)
|
||||
@ -643,6 +738,17 @@ static int cel_dx010_lpc_drv_probe(struct platform_device *pdev)
|
||||
cpld_data->i2c_adapter[portid_count-1] =
|
||||
cel_dx010_i2c_init(pdev, portid_count);
|
||||
|
||||
/* Enable INT0 interrupt register */
|
||||
outb(inb(CPLD4_INT0_MSK) & 0xf8, CPLD4_INT0_MSK);
|
||||
|
||||
/* Enable modprs interrupt register */
|
||||
outb(0, ABS_INT_MSK0108);
|
||||
outb(0, ABS_INT_MSK0910);
|
||||
outb(0, ABS_INT_MSK1118);
|
||||
outb(0, ABS_INT_MSK1921);
|
||||
outb(0, ABS_INT_MSK2229);
|
||||
outb(0, ABS_INT_MSK3032);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -683,7 +789,7 @@ void cel_dx010_lpc_exit(void)
|
||||
module_init(cel_dx010_lpc_init);
|
||||
module_exit(cel_dx010_lpc_exit);
|
||||
|
||||
MODULE_AUTHOR("Abhisit Sangjan <asang@celestica.com>");
|
||||
MODULE_AUTHOR("Pariwat Leamsumran <pleamsum@celestica.com>");
|
||||
MODULE_AUTHOR("Pradchaya P <pphuchar@celestica.com>");
|
||||
MODULE_VERSION("1.0.1");
|
||||
MODULE_DESCRIPTION("Celestica SeaStone DX010 LPC Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user