From 392899682f0d8b5f84f5635b0868a51f64177198 Mon Sep 17 00:00:00 2001 From: Maxime Lorrillere Date: Fri, 20 May 2022 14:11:06 -0700 Subject: [PATCH] [Arista] Add support for Wolverine linecards (#8887) Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs Co-authored-by: Maxime Lorrillere --- .../Arista-7800R3A-36D-C72 | 1 + .../0/context_config.json | 25 + .../0/j2p-a7800r3a-36d-36x400G.config.bcm | 996 ++++++++++++++++++ .../Arista-7800R3A-36D2-C72/0/port_config.ini | 39 + .../Arista-7800R3A-36D2-C72/0/sai.profile | 2 + .../1/context_config.json | 1 + .../1/j2p-a7800r3a-36d-36x400G.config.bcm | 996 ++++++++++++++++++ .../Arista-7800R3A-36D2-C72/1/port_config.ini | 39 + .../Arista-7800R3A-36D2-C72/1/sai.profile | 1 + .../Arista-7800R3A-36D2-C72/port_config.ini | 77 ++ .../Arista-7800R3A-36DM2-C72 | 1 + .../Arista-7800R3A-36P-C72 | 1 + .../Arista-7800R3AK-36D2-C72 | 1 + .../Arista-7800R3AK-36DM2-C72 | 1 + .../x86_64-arista_7800r3a_36d2_lc/asic.conf | 3 + .../chassisdb.conf | 2 + .../x86_64-arista_7800r3a_36d2_lc/pcie.yaml | 246 +++++ .../platform_asic | 1 + .../platform_env.conf | 2 + .../x86_64-arista_7800r3a_36d2_lc/plugins | 1 + .../pmon_daemon_control.json | 1 + .../sensors.conf | 6 + .../system_health_monitoring_config.json | 1 + .../thermal_policy.json | 1 + device/arista/x86_64-arista_7800r3a_36d_lc | 1 + device/arista/x86_64-arista_7800r3a_36dm2_lc | 1 + device/arista/x86_64-arista_7800r3a_36p_lc | 1 + device/arista/x86_64-arista_7800r3ak_36d2_lc | 1 + device/arista/x86_64-arista_7800r3ak_36dm2_lc | 1 + files/Aboot/boot0.j2 | 16 + 30 files changed, 2466 insertions(+) create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C72 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/port_config.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/sai.profile create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/port_config.ini create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/sai.profile create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/port_config.ini create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C72 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C72 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C72 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C72 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/asic.conf create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/chassisdb.conf create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/pcie.yaml create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/platform_asic create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/platform_env.conf create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/plugins create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/pmon_daemon_control.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/sensors.conf create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/system_health_monitoring_config.json create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/thermal_policy.json create mode 120000 device/arista/x86_64-arista_7800r3a_36d_lc create mode 120000 device/arista/x86_64-arista_7800r3a_36dm2_lc create mode 120000 device/arista/x86_64-arista_7800r3a_36p_lc create mode 120000 device/arista/x86_64-arista_7800r3ak_36d2_lc create mode 120000 device/arista/x86_64-arista_7800r3ak_36dm2_lc diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C72 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C72 new file mode 120000 index 0000000000..762deebff6 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C72 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C72 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/context_config.json new file mode 100644 index 0000000000..2c126e7189 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/context_config.json @@ -0,0 +1,25 @@ +{ + "CONTEXTS": [ + { + "guid" : 0, + "name" : "syncd", + "dbAsic" : "ASIC_DB", + "dbCounters" : "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState" : "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index" : 0, + "hwinfo" : "06:00.0" + }, + { + "index" : 1, + "hwinfo" : "07:00.0" + } + ] + } + ] +} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 0000000000..8d13e2ca43 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,996 @@ +soc_family=BCM8885X + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CGE18:core_1.1 +ucode_port_2=CGE19:core_1.2 +ucode_port_3=CGE20:core_1.3 +ucode_port_4=CGE21:core_1.4 +ucode_port_5=CGE22:core_1.5 +ucode_port_6=CGE23:core_1.6 +ucode_port_7=CGE24:core_1.7 +ucode_port_8=CGE25:core_1.8 +ucode_port_9=CGE26:core_1.9 +ucode_port_10=CGE27:core_1.10 +ucode_port_11=CGE28:core_1.11 +ucode_port_12=CGE29:core_1.12 +ucode_port_13=CGE30:core_1.13 +ucode_port_14=CGE31:core_1.14 +ucode_port_15=CGE32:core_1.15 +ucode_port_16=CGE33:core_1.16 +ucode_port_17=CGE34:core_1.17 +ucode_port_18=CGE35:core_1.18 + +ucode_port_19=CGE16:core_0.19 +ucode_port_20=CGE17:core_0.20 +ucode_port_21=CGE14:core_0.21 +ucode_port_22=CGE15:core_0.22 +ucode_port_23=CGE12:core_0.23 +ucode_port_24=CGE13:core_0.24 +ucode_port_25=CGE10:core_0.25 +ucode_port_26=CGE11:core_0.26 +ucode_port_27=CGE8:core_0.27 +ucode_port_28=CGE9:core_0.28 +ucode_port_29=CGE6:core_0.29 +ucode_port_30=CGE7:core_0.30 +ucode_port_31=CGE4:core_0.31 +ucode_port_32=CGE5:core_0.32 +ucode_port_33=CGE2:core_0.33 +ucode_port_34=CGE3:core_0.34 +ucode_port_35=CGE0:core_0.35 +ucode_port_36=CGE1:core_0.36 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=1 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=1 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=1 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=1 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=0 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_20=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_23=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_24=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_34=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_35=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_36=nrz:-8:89:-29:0:0:0 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/port_config.ini new file mode 100644 index 0000000000..25e9fb6226 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/port_config.ini @@ -0,0 +1,39 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet0 72,73,74,75 Ethernet1/1 1 Ext 100000 Eth0-ASIC0 1 1 8 +Ethernet4 76,77,78,79 Ethernet1/5 1 Ext 100000 Eth4-ASIC0 1 2 8 +Ethernet8 80,81,82,83 Ethernet2/1 2 Ext 100000 Eth8-ASIC0 1 3 8 +Ethernet12 84,85,86,87 Ethernet2/5 2 Ext 100000 Eth12-ASIC0 1 4 8 +Ethernet16 88,89,90,91 Ethernet3/1 3 Ext 100000 Eth16-ASIC0 1 5 8 +Ethernet20 92,93,94,95 Ethernet3/5 3 Ext 100000 Eth20-ASIC0 1 6 8 +Ethernet24 96,97,98,99 Ethernet4/1 4 Ext 100000 Eth24-ASIC0 1 7 8 +Ethernet28 100,101,102,103 Ethernet4/5 4 Ext 100000 Eth28-ASIC0 1 8 8 +Ethernet32 104,105,106,107 Ethernet5/1 5 Ext 100000 Eth32-ASIC0 1 9 8 +Ethernet36 108,109,110,111 Ethernet5/5 5 Ext 100000 Eth36-ASIC0 1 10 8 +Ethernet40 112,113,114,115 Ethernet6/1 6 Ext 100000 Eth40-ASIC0 1 11 8 +Ethernet44 116,117,118,119 Ethernet6/5 6 Ext 100000 Eth44-ASIC0 1 12 8 +Ethernet48 120,121,122,123 Ethernet7/1 7 Ext 100000 Eth48-ASIC0 1 13 8 +Ethernet52 124,125,126,127 Ethernet7/5 7 Ext 100000 Eth52-ASIC0 1 14 8 +Ethernet56 128,129,130,131 Ethernet8/1 8 Ext 100000 Eth56-ASIC0 1 15 8 +Ethernet60 132,133,134,135 Ethernet8/5 8 Ext 100000 Eth60-ASIC0 1 16 8 +Ethernet64 136,137,138,139 Ethernet9/1 9 Ext 100000 Eth64-ASIC0 1 17 8 +Ethernet68 140,141,142,143 Ethernet9/5 9 Ext 100000 Eth68-ASIC0 1 18 8 +Ethernet72 64,65,66,67 Ethernet10/1 10 Ext 100000 Eth72-ASIC0 0 19 8 +Ethernet76 68,69,70,71 Ethernet10/5 10 Ext 100000 Eth76-ASIC0 0 20 8 +Ethernet80 56,57,58,59 Ethernet11/1 11 Ext 100000 Eth80-ASIC0 0 21 8 +Ethernet84 60,61,62,63 Ethernet11/5 11 Ext 100000 Eth84-ASIC0 0 22 8 +Ethernet88 48,49,50,51 Ethernet12/1 12 Ext 100000 Eth88-ASIC0 0 23 8 +Ethernet92 52,53,54,55 Ethernet12/5 12 Ext 100000 Eth92-ASIC0 0 24 8 +Ethernet96 40,41,42,43 Ethernet13/1 13 Ext 100000 Eth96-ASIC0 0 25 8 +Ethernet100 44,45,46,47 Ethernet13/5 13 Ext 100000 Eth100-ASIC0 0 26 8 +Ethernet104 32,33,34,35 Ethernet14/1 14 Ext 100000 Eth104-ASIC0 0 27 8 +Ethernet108 36,37,38,39 Ethernet14/5 14 Ext 100000 Eth108-ASIC0 0 28 8 +Ethernet112 24,25,26,27 Ethernet15/1 15 Ext 100000 Eth112-ASIC0 0 29 8 +Ethernet116 28,29,30,31 Ethernet15/5 15 Ext 100000 Eth116-ASIC0 0 30 8 +Ethernet120 16,17,18,19 Ethernet16/1 16 Ext 100000 Eth120-ASIC0 0 31 8 +Ethernet124 20,21,22,23 Ethernet16/5 16 Ext 100000 Eth124-ASIC0 0 32 8 +Ethernet128 8,9,10,11 Ethernet17/1 17 Ext 100000 Eth128-ASIC0 0 33 8 +Ethernet132 12,13,14,15 Ethernet17/5 17 Ext 100000 Eth132-ASIC0 0 34 8 +Ethernet136 0,1,2,3 Ethernet18/1 18 Ext 100000 Eth136-ASIC0 0 35 8 +Ethernet140 4,5,6,7 Ethernet18/5 18 Ext 100000 Eth140-ASIC0 0 36 8 +Ethernet-Rec0 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC0 0 221 8 +Ethernet-IB0 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC0 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/sai.profile new file mode 100644 index 0000000000..894b300ad7 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/sai.profile @@ -0,0 +1,2 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/j2p-a7800r3a-36d-36x400G.config.bcm + diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/context_config.json new file mode 120000 index 0000000000..3db0e8ed3d --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/context_config.json @@ -0,0 +1 @@ +../0/context_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 0000000000..84b62055b9 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,996 @@ +soc_family=BCM8885X + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CGE18:core_1.1 +ucode_port_2=CGE19:core_1.2 +ucode_port_3=CGE20:core_1.3 +ucode_port_4=CGE21:core_1.4 +ucode_port_5=CGE22:core_1.5 +ucode_port_6=CGE23:core_1.6 +ucode_port_7=CGE24:core_1.7 +ucode_port_8=CGE25:core_1.8 +ucode_port_9=CGE26:core_1.9 +ucode_port_10=CGE27:core_1.10 +ucode_port_11=CGE28:core_1.11 +ucode_port_12=CGE29:core_1.12 +ucode_port_13=CGE30:core_1.13 +ucode_port_14=CGE31:core_1.14 +ucode_port_15=CGE32:core_1.15 +ucode_port_16=CGE33:core_1.16 +ucode_port_17=CGE34:core_1.17 +ucode_port_18=CGE35:core_1.18 + +ucode_port_19=CGE16:core_0.19 +ucode_port_20=CGE17:core_0.20 +ucode_port_21=CGE14:core_0.21 +ucode_port_22=CGE15:core_0.22 +ucode_port_23=CGE12:core_0.23 +ucode_port_24=CGE13:core_0.24 +ucode_port_25=CGE10:core_0.25 +ucode_port_26=CGE11:core_0.26 +ucode_port_27=CGE8:core_0.27 +ucode_port_28=CGE9:core_0.28 +ucode_port_29=CGE6:core_0.29 +ucode_port_30=CGE7:core_0.30 +ucode_port_31=CGE4:core_0.31 +ucode_port_32=CGE5:core_0.32 +ucode_port_33=CGE2:core_0.33 +ucode_port_34=CGE3:core_0.34 +ucode_port_35=CGE0:core_0.35 +ucode_port_36=CGE1:core_0.36 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=0 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=0 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=0 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=0 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=1 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_20=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_23=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_24=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_34=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_35=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_36=nrz:-7:85:-25:0:0:0 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/port_config.ini new file mode 100644 index 0000000000..d5b9419c95 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/port_config.ini @@ -0,0 +1,39 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet144 72,73,74,75 Ethernet19/1 19 Ext 100000 Eth144-ASIC1 1 1 8 +Ethernet148 76,77,78,79 Ethernet19/5 19 Ext 100000 Eth148-ASIC1 1 2 8 +Ethernet152 80,81,82,83 Ethernet20/1 20 Ext 100000 Eth152-ASIC1 1 3 8 +Ethernet156 84,85,86,87 Ethernet20/5 20 Ext 100000 Eth156-ASIC1 1 4 8 +Ethernet160 88,89,90,91 Ethernet21/1 21 Ext 100000 Eth160-ASIC1 1 5 8 +Ethernet164 92,93,94,95 Ethernet21/5 21 Ext 100000 Eth164-ASIC1 1 6 8 +Ethernet168 96,97,98,99 Ethernet22/1 22 Ext 100000 Eth168-ASIC1 1 7 8 +Ethernet172 100,101,102,103 Ethernet22/5 22 Ext 100000 Eth172-ASIC1 1 8 8 +Ethernet176 104,105,106,107 Ethernet23/1 23 Ext 100000 Eth176-ASIC1 1 9 8 +Ethernet180 108,109,110,111 Ethernet23/5 23 Ext 100000 Eth180-ASIC1 1 10 8 +Ethernet184 112,113,114,115 Ethernet24/1 24 Ext 100000 Eth184-ASIC1 1 11 8 +Ethernet188 116,117,118,119 Ethernet24/5 24 Ext 100000 Eth188-ASIC1 1 12 8 +Ethernet192 120,121,122,123 Ethernet25/1 25 Ext 100000 Eth192-ASIC1 1 13 8 +Ethernet196 124,125,126,127 Ethernet25/5 25 Ext 100000 Eth196-ASIC1 1 14 8 +Ethernet200 128,129,130,131 Ethernet26/1 26 Ext 100000 Eth200-ASIC1 1 15 8 +Ethernet204 132,133,134,135 Ethernet26/5 26 Ext 100000 Eth204-ASIC1 1 16 8 +Ethernet208 136,137,138,139 Ethernet27/1 27 Ext 100000 Eth208-ASIC1 1 17 8 +Ethernet212 140,141,142,143 Ethernet27/5 27 Ext 100000 Eth212-ASIC1 1 18 8 +Ethernet216 64,65,66,67 Ethernet28/1 28 Ext 100000 Eth216-ASIC1 0 19 8 +Ethernet220 68,69,70,71 Ethernet28/5 28 Ext 100000 Eth220-ASIC1 0 20 8 +Ethernet224 56,57,58,59 Ethernet29/1 29 Ext 100000 Eth224-ASIC1 0 21 8 +Ethernet228 60,61,62,63 Ethernet29/5 29 Ext 100000 Eth228-ASIC1 0 22 8 +Ethernet232 48,49,50,51 Ethernet30/1 30 Ext 100000 Eth232-ASIC1 0 23 8 +Ethernet236 52,53,54,55 Ethernet30/5 30 Ext 100000 Eth236-ASIC1 0 24 8 +Ethernet240 40,41,42,43 Ethernet31/1 31 Ext 100000 Eth240-ASIC1 0 25 8 +Ethernet244 44,45,46,47 Ethernet31/5 31 Ext 100000 Eth244-ASIC1 0 26 8 +Ethernet248 32,33,34,35 Ethernet32/1 32 Ext 100000 Eth248-ASIC1 0 27 8 +Ethernet252 36,37,38,39 Ethernet32/5 32 Ext 100000 Eth252-ASIC1 0 28 8 +Ethernet256 24,25,26,27 Ethernet33/1 33 Ext 100000 Eth256-ASIC1 0 29 8 +Ethernet260 28,29,30,31 Ethernet33/5 33 Ext 100000 Eth260-ASIC1 0 30 8 +Ethernet264 16,17,18,19 Ethernet34/1 34 Ext 100000 Eth264-ASIC1 0 31 8 +Ethernet268 20,21,22,23 Ethernet34/5 34 Ext 100000 Eth268-ASIC1 0 32 8 +Ethernet272 8,9,10,11 Ethernet35/1 35 Ext 100000 Eth272-ASIC1 0 33 8 +Ethernet276 12,13,14,15 Ethernet35/5 35 Ext 100000 Eth276-ASIC1 0 34 8 +Ethernet280 0,1,2,3 Ethernet36/1 36 Ext 100000 Eth280-ASIC1 0 35 8 +Ethernet284 4,5,6,7 Ethernet36/5 36 Ext 100000 Eth284-ASIC1 0 36 8 +Ethernet-Rec1 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC1 0 221 8 +Ethernet-IB1 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC1 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/sai.profile new file mode 120000 index 0000000000..1e172f3e07 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/sai.profile @@ -0,0 +1 @@ +../0/sai.profile \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/port_config.ini new file mode 100644 index 0000000000..1144628619 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/port_config.ini @@ -0,0 +1,77 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet0 72,73,74,75 Ethernet1/1 1 Ext 100000 Eth0-ASIC0 1 1 8 +Ethernet4 76,77,78,79 Ethernet1/5 1 Ext 100000 Eth4-ASIC0 1 2 8 +Ethernet8 80,81,82,83 Ethernet2/1 2 Ext 100000 Eth8-ASIC0 1 3 8 +Ethernet12 84,85,86,87 Ethernet2/5 2 Ext 100000 Eth12-ASIC0 1 4 8 +Ethernet16 88,89,90,91 Ethernet3/1 3 Ext 100000 Eth16-ASIC0 1 5 8 +Ethernet20 92,93,94,95 Ethernet3/5 3 Ext 100000 Eth20-ASIC0 1 6 8 +Ethernet24 96,97,98,99 Ethernet4/1 4 Ext 100000 Eth24-ASIC0 1 7 8 +Ethernet28 100,101,102,103 Ethernet4/5 4 Ext 100000 Eth28-ASIC0 1 8 8 +Ethernet32 104,105,106,107 Ethernet5/1 5 Ext 100000 Eth32-ASIC0 1 9 8 +Ethernet36 108,109,110,111 Ethernet5/5 5 Ext 100000 Eth36-ASIC0 1 10 8 +Ethernet40 112,113,114,115 Ethernet6/1 6 Ext 100000 Eth40-ASIC0 1 11 8 +Ethernet44 116,117,118,119 Ethernet6/5 6 Ext 100000 Eth44-ASIC0 1 12 8 +Ethernet48 120,121,122,123 Ethernet7/1 7 Ext 100000 Eth48-ASIC0 1 13 8 +Ethernet52 124,125,126,127 Ethernet7/5 7 Ext 100000 Eth52-ASIC0 1 14 8 +Ethernet56 128,129,130,131 Ethernet8/1 8 Ext 100000 Eth56-ASIC0 1 15 8 +Ethernet60 132,133,134,135 Ethernet8/5 8 Ext 100000 Eth60-ASIC0 1 16 8 +Ethernet64 136,137,138,139 Ethernet9/1 9 Ext 100000 Eth64-ASIC0 1 17 8 +Ethernet68 140,141,142,143 Ethernet9/5 9 Ext 100000 Eth68-ASIC0 1 18 8 +Ethernet72 64,65,66,67 Ethernet10/1 10 Ext 100000 Eth72-ASIC0 0 19 8 +Ethernet76 68,69,70,71 Ethernet10/5 10 Ext 100000 Eth76-ASIC0 0 20 8 +Ethernet80 56,57,58,59 Ethernet11/1 11 Ext 100000 Eth80-ASIC0 0 21 8 +Ethernet84 60,61,62,63 Ethernet11/5 11 Ext 100000 Eth84-ASIC0 0 22 8 +Ethernet88 48,49,50,51 Ethernet12/1 12 Ext 100000 Eth88-ASIC0 0 23 8 +Ethernet92 52,53,54,55 Ethernet12/5 12 Ext 100000 Eth92-ASIC0 0 24 8 +Ethernet96 40,41,42,43 Ethernet13/1 13 Ext 100000 Eth96-ASIC0 0 25 8 +Ethernet100 44,45,46,47 Ethernet13/5 13 Ext 100000 Eth100-ASIC0 0 26 8 +Ethernet104 32,33,34,35 Ethernet14/1 14 Ext 100000 Eth104-ASIC0 0 27 8 +Ethernet108 36,37,38,39 Ethernet14/5 14 Ext 100000 Eth108-ASIC0 0 28 8 +Ethernet112 24,25,26,27 Ethernet15/1 15 Ext 100000 Eth112-ASIC0 0 29 8 +Ethernet116 28,29,30,31 Ethernet15/5 15 Ext 100000 Eth116-ASIC0 0 30 8 +Ethernet120 16,17,18,19 Ethernet16/1 16 Ext 100000 Eth120-ASIC0 0 31 8 +Ethernet124 20,21,22,23 Ethernet16/5 16 Ext 100000 Eth124-ASIC0 0 32 8 +Ethernet128 8,9,10,11 Ethernet17/1 17 Ext 100000 Eth128-ASIC0 0 33 8 +Ethernet132 12,13,14,15 Ethernet17/5 17 Ext 100000 Eth132-ASIC0 0 34 8 +Ethernet136 0,1,2,3 Ethernet18/1 18 Ext 100000 Eth136-ASIC0 0 35 8 +Ethernet140 4,5,6,7 Ethernet18/5 18 Ext 100000 Eth140-ASIC0 0 36 8 +Ethernet-Rec0 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC0 0 221 8 +Ethernet-IB0 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC0 1 222 8 +Ethernet144 72,73,74,75 Ethernet19/1 19 Ext 100000 Eth144-ASIC1 1 1 8 +Ethernet148 76,77,78,79 Ethernet19/5 19 Ext 100000 Eth148-ASIC1 1 2 8 +Ethernet152 80,81,82,83 Ethernet20/1 20 Ext 100000 Eth152-ASIC1 1 3 8 +Ethernet156 84,85,86,87 Ethernet20/5 20 Ext 100000 Eth156-ASIC1 1 4 8 +Ethernet160 88,89,90,91 Ethernet21/1 21 Ext 100000 Eth160-ASIC1 1 5 8 +Ethernet164 92,93,94,95 Ethernet21/5 21 Ext 100000 Eth164-ASIC1 1 6 8 +Ethernet168 96,97,98,99 Ethernet22/1 22 Ext 100000 Eth168-ASIC1 1 7 8 +Ethernet172 100,101,102,103 Ethernet22/5 22 Ext 100000 Eth172-ASIC1 1 8 8 +Ethernet176 104,105,106,107 Ethernet23/1 23 Ext 100000 Eth176-ASIC1 1 9 8 +Ethernet180 108,109,110,111 Ethernet23/5 23 Ext 100000 Eth180-ASIC1 1 10 8 +Ethernet184 112,113,114,115 Ethernet24/1 24 Ext 100000 Eth184-ASIC1 1 11 8 +Ethernet188 116,117,118,119 Ethernet24/5 24 Ext 100000 Eth188-ASIC1 1 12 8 +Ethernet192 120,121,122,123 Ethernet25/1 25 Ext 100000 Eth192-ASIC1 1 13 8 +Ethernet196 124,125,126,127 Ethernet25/5 25 Ext 100000 Eth196-ASIC1 1 14 8 +Ethernet200 128,129,130,131 Ethernet26/1 26 Ext 100000 Eth200-ASIC1 1 15 8 +Ethernet204 132,133,134,135 Ethernet26/5 26 Ext 100000 Eth204-ASIC1 1 16 8 +Ethernet208 136,137,138,139 Ethernet27/1 27 Ext 100000 Eth208-ASIC1 1 17 8 +Ethernet212 140,141,142,143 Ethernet27/5 27 Ext 100000 Eth212-ASIC1 1 18 8 +Ethernet216 64,65,66,67 Ethernet28/1 28 Ext 100000 Eth216-ASIC1 0 19 8 +Ethernet220 68,69,70,71 Ethernet28/5 28 Ext 100000 Eth220-ASIC1 0 20 8 +Ethernet224 56,57,58,59 Ethernet29/1 29 Ext 100000 Eth224-ASIC1 0 21 8 +Ethernet228 60,61,62,63 Ethernet29/5 29 Ext 100000 Eth228-ASIC1 0 22 8 +Ethernet232 48,49,50,51 Ethernet30/1 30 Ext 100000 Eth232-ASIC1 0 23 8 +Ethernet236 52,53,54,55 Ethernet30/5 30 Ext 100000 Eth236-ASIC1 0 24 8 +Ethernet240 40,41,42,43 Ethernet31/1 31 Ext 100000 Eth240-ASIC1 0 25 8 +Ethernet244 44,45,46,47 Ethernet31/5 31 Ext 100000 Eth244-ASIC1 0 26 8 +Ethernet248 32,33,34,35 Ethernet32/1 32 Ext 100000 Eth248-ASIC1 0 27 8 +Ethernet252 36,37,38,39 Ethernet32/5 32 Ext 100000 Eth252-ASIC1 0 28 8 +Ethernet256 24,25,26,27 Ethernet33/1 33 Ext 100000 Eth256-ASIC1 0 29 8 +Ethernet260 28,29,30,31 Ethernet33/5 33 Ext 100000 Eth260-ASIC1 0 30 8 +Ethernet264 16,17,18,19 Ethernet34/1 34 Ext 100000 Eth264-ASIC1 0 31 8 +Ethernet268 20,21,22,23 Ethernet34/5 34 Ext 100000 Eth268-ASIC1 0 32 8 +Ethernet272 8,9,10,11 Ethernet35/1 35 Ext 100000 Eth272-ASIC1 0 33 8 +Ethernet276 12,13,14,15 Ethernet35/5 35 Ext 100000 Eth276-ASIC1 0 34 8 +Ethernet280 0,1,2,3 Ethernet36/1 36 Ext 100000 Eth280-ASIC1 0 35 8 +Ethernet284 4,5,6,7 Ethernet36/5 36 Ext 100000 Eth284-ASIC1 0 36 8 +Ethernet-Rec1 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC1 0 221 8 +Ethernet-IB1 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC1 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C72 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C72 new file mode 120000 index 0000000000..762deebff6 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C72 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C72 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C72 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C72 new file mode 120000 index 0000000000..762deebff6 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C72 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C72 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C72 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C72 new file mode 120000 index 0000000000..762deebff6 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C72 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C72 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C72 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C72 new file mode 120000 index 0000000000..762deebff6 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C72 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C72 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/asic.conf b/device/arista/x86_64-arista_7800r3a_36d2_lc/asic.conf new file mode 100644 index 0000000000..3e123ed50a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/asic.conf @@ -0,0 +1,3 @@ +NUM_ASIC=2 +DEV_ID_ASIC_0=06:00.0 +DEV_ID_ASIC_1=07:00.0 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/chassisdb.conf b/device/arista/x86_64-arista_7800r3a_36d2_lc/chassisdb.conf new file mode 100644 index 0000000000..e259cf7421 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/chassisdb.conf @@ -0,0 +1,2 @@ +midplane_subnet=127.100.0.0/16 +chassis_db_address=127.100.1.1 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/pcie.yaml b/device/arista/x86_64-arista_7800r3a_36d2_lc/pcie.yaml new file mode 100644 index 0000000000..4b4481f315 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/pcie.yaml @@ -0,0 +1,246 @@ +- bus: '00' + dev: '00' + fn: '0' + id: '1450' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Root Complex' +- bus: '00' + dev: '00' + fn: '2' + id: '1451' + name: 'IOMMU: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) I/O + Memory Management Unit' +- bus: '00' + dev: '01' + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: '01' + fn: '4' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '01' + fn: '5' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '01' + fn: '6' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '02' + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: '03' + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: '03' + fn: '1' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '03' + fn: '2' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '03' + fn: '3' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '03' + fn: '4' + id: '1453' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + PCIe GPP Bridge' +- bus: '00' + dev: '04' + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: '07' + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: '07' + fn: '1' + id: '1454' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Internal PCIe GPP Bridge 0 to Bus B' +- bus: '00' + dev: 08 + fn: '0' + id: '1452' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) + PCIe Dummy Host Bridge' +- bus: '00' + dev: 08 + fn: '1' + id: '1454' + name: 'PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Internal PCIe GPP Bridge 0 to Bus B' +- bus: '00' + dev: '14' + fn: '0' + id: 790b + name: 'SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 59)' +- bus: '00' + dev: '14' + fn: '3' + id: 790e + name: 'ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 51)' +- bus: '00' + dev: '18' + fn: '0' + id: '1460' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 0' +- bus: '00' + dev: '18' + fn: '1' + id: '1461' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 1' +- bus: '00' + dev: '18' + fn: '2' + id: '1462' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 2' +- bus: '00' + dev: '18' + fn: '3' + id: '1463' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 3' +- bus: '00' + dev: '18' + fn: '4' + id: '1464' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 4' +- bus: '00' + dev: '18' + fn: '5' + id: '1465' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 5' +- bus: '00' + dev: '18' + fn: '6' + id: '1466' + name: 'Host bridge: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + Data Fabric: Device 18h; Function 6' +- bus: '00' + dev: '18' + fn: '7' + id: '0001' + name: 'Host bridge: Arista Networks, Inc. Device 0001' +- bus: '04' + dev: '00' + fn: '0' + id: '8717' + name: 'PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen + 3 (8.0 GT/s) Switch with DMA (rev ca)' +- bus: '05' + dev: '03' + fn: '0' + id: '8717' + name: 'PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen + 3 (8.0 GT/s) Switch with DMA (rev ca)' +- bus: '05' + dev: '04' + fn: '0' + id: '8717' + name: 'PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen + 3 (8.0 GT/s) Switch with DMA (rev ca)' +- bus: '05' + dev: '05' + fn: '0' + id: '8717' + name: 'PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen + 3 (8.0 GT/s) Switch with DMA (rev ca)' +- bus: '06' + dev: '00' + fn: '0' + id: '8852' + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device 8852 (rev 02)' +- bus: '07' + dev: '00' + fn: '0' + id: '8852' + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device 8852 (rev 02)' +- bus: 08 + dev: '00' + fn: '0' + id: '0001' + name: 'System peripheral: Arista Networks, Inc. Device 0001 (rev 01)' +- bus: '10' + dev: '00' + fn: '0' + id: '1682' + name: 'Ethernet controller: Broadcom Inc. and subsidiaries NetXtreme BCM57762 Gigabit + Ethernet PCIe (rev 01)' +- bus: '11' + dev: '00' + fn: '0' + id: 145a + name: 'Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] + Zeppelin/Raven/Raven2 PCIe Dummy Function' +- bus: '11' + dev: '00' + fn: '2' + id: '1456' + name: 'Encryption controller: Advanced Micro Devices, Inc. [AMD] Family 17h (Models + 00h-0fh) Platform Security Processor' +- bus: '11' + dev: '00' + fn: '3' + id: 145f + name: 'USB controller: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host + controller' +- bus: '12' + dev: '00' + fn: '0' + id: '1455' + name: 'Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] + Zeppelin/Renoir PCIe Dummy Function' +- bus: '12' + dev: '00' + fn: '1' + id: '1468' + name: 'Encryption controller: Advanced Micro Devices, Inc. [AMD] Zeppelin Cryptographic + Coprocessor NTBCCP' +- bus: '12' + dev: '00' + fn: '2' + id: '7901' + name: 'SATA controller: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI + mode] (rev 51)' +- bus: '12' + dev: '00' + fn: '3' + id: '1457' + name: 'Audio device: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) + HD Audio Controller' diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_asic b/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_asic new file mode 100644 index 0000000000..9ba24ca3e7 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_env.conf b/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_env.conf new file mode 100644 index 0000000000..558fb7393f --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/platform_env.conf @@ -0,0 +1,2 @@ +usemsi=1 +dmasize=64M diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/plugins b/device/arista/x86_64-arista_7800r3a_36d2_lc/plugins new file mode 120000 index 0000000000..5fbbf98a62 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins/ \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/pmon_daemon_control.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/pmon_daemon_control.json new file mode 120000 index 0000000000..26ee0d4d13 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control_linecard.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/sensors.conf b/device/arista/x86_64-arista_7800r3a_36d2_lc/sensors.conf new file mode 100644 index 0000000000..d2b272483e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/sensors.conf @@ -0,0 +1,6 @@ +# autogenerated by arista + +chip "k10temp-pci-00c3" + label temp1 "Cpu temp sensor" + set temp1_max 90 + set temp1_crit 95 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/system_health_monitoring_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/system_health_monitoring_config.json new file mode 120000 index 0000000000..035cde619c --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config_linecard.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/thermal_policy.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/thermal_policy.json new file mode 120000 index 0000000000..7c7982deaf --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy_linecard.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d_lc b/device/arista/x86_64-arista_7800r3a_36d_lc new file mode 120000 index 0000000000..50e843fb31 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d_lc @@ -0,0 +1 @@ +x86_64-arista_7800r3a_36d2_lc \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36dm2_lc b/device/arista/x86_64-arista_7800r3a_36dm2_lc new file mode 120000 index 0000000000..50e843fb31 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36dm2_lc @@ -0,0 +1 @@ +x86_64-arista_7800r3a_36d2_lc \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36p_lc b/device/arista/x86_64-arista_7800r3a_36p_lc new file mode 120000 index 0000000000..50e843fb31 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36p_lc @@ -0,0 +1 @@ +x86_64-arista_7800r3a_36d2_lc \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3ak_36d2_lc b/device/arista/x86_64-arista_7800r3ak_36d2_lc new file mode 120000 index 0000000000..50e843fb31 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3ak_36d2_lc @@ -0,0 +1 @@ +x86_64-arista_7800r3a_36d2_lc \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3ak_36dm2_lc b/device/arista/x86_64-arista_7800r3ak_36dm2_lc new file mode 120000 index 0000000000..50e843fb31 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3ak_36dm2_lc @@ -0,0 +1 @@ +x86_64-arista_7800r3a_36d2_lc \ No newline at end of file diff --git a/files/Aboot/boot0.j2 b/files/Aboot/boot0.j2 index 2510695d13..5fe64b6884 100644 --- a/files/Aboot/boot0.j2 +++ b/files/Aboot/boot0.j2 @@ -558,6 +558,22 @@ write_platform_specific_cmdline() { aboot_machine=arista_7800r3_48cqm2_lc sonic_mode="$linecard_mode" fi + if [ "$sid" = "WolverineQCpu" ]; then + aboot_machine=arista_7800r3a_36d2_lc + sonic_mode="$linecard_mode" + fi + if [ "$sid" = "WolverineQCpuBk" ]; then + aboot_machine=arista_7800r3ak_36d2_lc + sonic_mode="$linecard_mode" + fi + if [ "$sid" = "WolverineQCpuMs" ]; then + aboot_machine=arista_7800r3a_36dm2_lc + sonic_mode="$linecard_mode" + fi + if [ "$sid" = "WolverineQCpuBkMs" ]; then + aboot_machine=arista_7800r3ak_36dm2_lc + sonic_mode="$linecard_mode" + fi if [ "$sid" = "OtterLake" ]; then aboot_machine=arista_7800_sup flash_size=30000