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[devices]: As7312 54x add sfp rest and fan policy (#1464)

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* Update sonic-platform-modules-accton to lastest

Signed-off-by: roylee123 <roy_lee@accton.com>

* Install sonic-platform-common package in platform-monitor docker for ledd (#1330)

* Install sonic-platform-common package in platform-monitor docker for ledd

* Specify Python wheel dependencies in docker-platform-monitor.mk; Remove explicit specifications from Dockerfile.j2

* [platform] 1. Add QSFP reset control.
           2. Validate fan control monitoring.
Signed-off-by: roy_lee <roy_lee@accton.com>

* Replace tab by blanks.
Signed-off-by: roy_lee <roy_lee@accton.com>

* Resolve submodule conflicts.
Signed-off-by: roy_lee <roy_lee@accton.com>

* AS7312-54x, fix a indention error on sfputil.py.
Signed-off-by: roy_lee <roy_lee@accton.com>
This commit is contained in:
Roy Lee 2018-03-15 01:23:54 +08:00 committed by lguohan
parent aa845b7c6c
commit 33252a4320
1 changed files with 35 additions and 22 deletions
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57
device/accton/x86_64-accton_as7312_54x-r0/plugins/sfputil.py
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@ -26,10 +26,10 @@ class SfpUtil(SfpUtilBase):
_port_to_eeprom_mapping = {}
_cpld_mapping = {
0: "4-0060",
1: "5-0062",
2: "6-0064",
}
0: "4-0060",
1: "5-0062",
2: "6-0064",
}
_port_to_i2c_mapping = {
0: 18,
1: 19,
@ -137,29 +137,40 @@ class SfpUtil(SfpUtilBase):
SfpUtilBase.__init__(self)
# For port 48~51 are QSFP, here presumed they're all split to 4 lanes.
def get_cage_num(self, port_num):
cage_num = port_num
if (port_num >= self.QSFP_PORT_START):
cage_num = (port_num - self.QSFP_PORT_START)/4
cage_num = cage_num + self.QSFP_PORT_START
return cage_num
# For cage 0~23 and 48~51 are at cpld2, others are at cpld3.
def get_cpld_num(self, port_num):
cpld_i = 1
cage_num = self.get_cage_num(port_num)
if (port_num > 23 and port_num < self.QSFP_PORT_START):
cpld_i = 2
if (cage_num >= 52):
cpld_i = 2
return cpld_i
def get_presence(self, port_num):
# Check for invalid port_num
if port_num < self.port_start or port_num > self.port_end:
return False
# For cage 0~23 and 48~51 are at cpld2, others are at cpld3.
# For port 48~51 are QSFP, here presumed they are all broken-out to 4 lanes.
cage_num = port_num
cpld_i = 1
if (port_num > 23):
cpld_i = 2
if (port_num >= self.QSFP_PORT_START):
cpld_i = 1
cage_num = (port_num - self.QSFP_PORT_START)/4
cage_num = cage_num + self.QSFP_PORT_START
if (cage_num >= 52):
cpld_i = 2
cage_num = self.get_cage_num(port_num)
cpld_i = self.get_cpld_num(port_num)
cpld_ps = self._cpld_mapping[cpld_i]
path = "/sys/bus/i2c/devices/{0}/module_present_{1}"
port_ps = path.format(cpld_ps, cage_num+1)
try:
val_file = open(port_ps)
except IOError as e:
@ -185,16 +196,18 @@ class SfpUtil(SfpUtilBase):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False
path = "/sys/bus/i2c/devices/5-0062/module_reset_{0}"
port_ps = path.format(port_num+1)
cage_num = self.get_cage_num(port_num)
cpld_i = self.get_cpld_num(port_num)
cpld_ps = self._cpld_mapping[cpld_i]
path = "/sys/bus/i2c/devices/{0}/module_reset_{1}"
port_ps = path.format(cpld_ps, cage_num+1)
try:
reg_file = open(port_ps, 'w')
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False
reg_value = '1'
reg_value = '0'
reg_file.write(reg_value)
reg_file.close()