refactor bcm attribute checker (#1974)
* refactor bcm attribute checker * exclude phy_84752 and phy_84328 Signed-off-by: Guohan Lu <gulv@microsoft.com>
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674b58e2a2
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26850b351f
@ -10,29 +10,9 @@ def usage():
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sys.exit(1)
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sys.exit(1)
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def check_property(p):
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def check_property(p):
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if p in permitted_properties:
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if p in permitted_properties:
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return True
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return True
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# Try to remove trailing .<digits>
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if re.sub(r".\d+$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _<digits>.<digits>
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if re.sub(r"_\d+.\d+$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _hg.<digits>
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if re.sub(r"_hg.0$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _[cx]e<digits>
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if re.sub(r"_[cx]e\d*$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _lane<digit>_<digits>
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if re.sub(r"_lane\d_\d+$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _lane<digit>_<digits>.<digits>
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if re.sub(r"_lane\d_\d+.\d+$", "", p) in permitted_properties:
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return True
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# Try to remove trailing _lane<digit>_[cx]e<digits>
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if re.sub(r"_lane\d_[cx]e\d+$", "", p) in permitted_properties:
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return True
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return False
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return False
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def check_file(file_name):
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def check_file(file_name):
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@ -45,12 +25,27 @@ def check_file(file_name):
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lineno = lineno + 1
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lineno = lineno + 1
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# Check both commented and uncommented lines
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# Check both commented and uncommented lines
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line = line.strip().lstrip('#').strip().lower()
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line = line.strip().lstrip('#').strip().lower()
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# Check if = in the line
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if line.find("=") == -1:
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if line.find("=") == -1:
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continue
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continue
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p = line.split("=", 1)[0]
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p = line.split("=", 1)[0]
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# Remove trailing "{<number>.<number>}"
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p = re.sub('{[0-9]+\.[0-9]+}', '', p)
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# Remove trailing unit ".<number>$"
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# Check if = in the line
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p = re.sub(r"\.[0-9]+$", '', p)
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# Remove trailing port name
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p = re.sub(r"_[cxg]e(\d+)?$", '', p)
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# Remove trailing port name example
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p = re.sub(r"_<port>$", '', p)
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# Remove trailing port number
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if p != "phy_84752" and p != "phy_84328":
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p = re.sub(r"_(port)?\d+$", '', p)
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# Remove trailing higig port
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p = re.sub(r"_hg$", '', p)
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# Remove trailing lane number
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p = re.sub(r"_lane\d+$", '', p)
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# Remove trailing "{<number>.<number>}$"
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p = re.sub(r"{[0-9]+\.[0-9]+}$", '', p)
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if not check_property(p):
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if not check_property(p):
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file_ok = False
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file_ok = False
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print("[line %d] Error: %s is not permitted" % (lineno, p))
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print("[line %d] Error: %s is not permitted" % (lineno, p))
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@ -7,6 +7,9 @@ bcm_stat_interval
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bcm_stat_jumbo
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bcm_stat_jumbo
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bcm_tunnel_term_compatible_mode
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bcm_tunnel_term_compatible_mode
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bcm_xlate_port_enable
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bcm_xlate_port_enable
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bcm56340_4x10
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bcm56340_2x10
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bcm56340_config
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cdma_timeout_usec
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cdma_timeout_usec
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core_clock_frequency
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core_clock_frequency
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ctr_evict_enable
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ctr_evict_enable
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@ -59,7 +62,7 @@ oversubscribe_mode
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parity_correction
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parity_correction
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parity_enable
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parity_enable
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pbmp_oversubscribe
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pbmp_oversubscribe
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pbmp_xport_xe
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pbmp_xport
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pci2eb_overrid
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pci2eb_overrid
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pfc_deadlock_seq_control
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pfc_deadlock_seq_control
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phy_84328
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phy_84328
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@ -69,31 +72,35 @@ phy_an_allow_pll_change_hg
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phy_an_c37
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phy_an_c37
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phy_an_c73
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phy_an_c73
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phy_an_fec
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phy_an_fec
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phy_automedium
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phy_aux_voltage_enable
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phy_aux_voltage_enable
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phy_chain_rx_lane_map_physical
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phy_chain_rx_lane_map_physical
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phy_chain_rx_polarity_flip_physical
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phy_chain_rx_polarity_flip_physical
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phy_chain_tx_lane_map_physical
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phy_chain_tx_lane_map_physical
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phy_chain_tx_polarity_flip_physical
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phy_chain_tx_polarity_flip_physical
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phy_ext_rom_boot
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phy_ext_rom_boot
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phy_fiber_pref
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phy_gearbox_enable
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phy_gearbox_enable
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phy_null
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phy_line_tx_mode
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phy_line_tx_mode
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phy_pcs_rx_polarity_flip
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phy_pcs_rx_polarity_flip
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phy_pcs_tx_polarity_flip
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phy_pcs_tx_polarity_flip
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phy_port_primary_and_offset
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phy_port_primary_and_offset
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phy_rx_polarity_flip
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phy_rx_polarity_flip
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phy_system_tx_mode
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phy_system_tx_mode
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phy_sgmii_autoneg
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phy_tx_polarity_flip
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phy_tx_polarity_flip
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phy_xaui_rx_polarity_flip
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phy_xaui_rx_polarity_flip
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phy_xaui_tx_polarity_flip
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phy_xaui_tx_polarity_flip
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physical_ports
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physical_ports
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port_init_autoneg
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port_init_autoneg
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port_init_cl72
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port_init_cl72
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port_init_cl72_hg
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port_init_speed
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port_init_speed_xe
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port_phy_addr
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port_phy_addr
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port_phy_clause
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port_phy_clause
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port_phy_id0
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port_phy_id0
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port_phy_id1
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port_phy_id1
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portgroup
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portmap
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portmap
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prbs_polynomial
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prbs_polynomial
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ptp_bs_fref
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ptp_bs_fref
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@ -113,7 +120,7 @@ serdes_firmware_mode
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serdes_if_type
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serdes_if_type
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serdes_pre_driver_current
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serdes_pre_driver_current
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serdes_preemphasis
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serdes_preemphasis
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serdes_rx_los_xe
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serdes_rx_los
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serdes_sgmii_m
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serdes_sgmii_m
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skip_L2_USER_ENTRY
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skip_L2_USER_ENTRY
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sram_scan_enable
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sram_scan_enable
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@ -129,6 +136,6 @@ tslam_intr_enable
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tslam_timeout_usec
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tslam_timeout_usec
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uplink_ports
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uplink_ports
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xgxs_lcpll_xtal_refclk
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xgxs_lcpll_xtal_refclk
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xgxs_pdetect_1
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xgxs_pdetect
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xgxs_rx_lane_map
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xgxs_rx_lane_map
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xgxs_tx_lane_map
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xgxs_tx_lane_map
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