[Nokia][Nokia-IXR7250E-36x100G & Nokia-IXR7250E-36x400G] Update BCM (#11577)

config to support ERSPAN egress mirror and also set flag to preserve ECN
This commit is contained in:
saksarav-nokia 2022-08-30 23:23:17 -04:00 committed by GitHub
parent 092e0394b5
commit 1e75abc274
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 168 additions and 54 deletions

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@ -8,7 +8,7 @@ dma_desc_aggregator_chain_length_max.BCM8885X=1000
dma_desc_aggregator_enable_specific_MDB_LPM.BCM8885X=1
dma_desc_aggregator_timeout_usec.BCM8885X=1000
dport_map_direct.BCM8885X=1
sai_postinit_cmd_file=/usr/share/sonic/hwsku/sai_postinit_cmd.soc
dtm_flow_mapping_mode_region_64.BCM8885X=3
dtm_flow_mapping_mode_region_65.BCM8885X=3
dtm_flow_mapping_mode_region_66.BCM8885X=3
@ -1532,12 +1532,50 @@ ucode_port_15.BCM8885X=CGE6:core_0.15
ucode_port_16.BCM8885X=CGE4:core_0.16
ucode_port_17.BCM8885X=CGE2:core_0.17
ucode_port_18.BCM8885X=CGE0:core_0.18
ucode_port_19.BCM8885X=RCY0:core_0.19
ucode_port_20.BCM8885X=RCY1:core_1.20
ucode_port_21.BCM8885X=OLP:core_1.21
ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100
ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101
ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102
ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103
ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104
ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105
ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106
ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107
ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108
ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109
ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110
ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111
ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112
ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113
ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114
ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115
ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116
ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117
ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118
ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119
ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120
ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121
ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122
ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123
ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124
ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125
ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126
ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127
ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128
ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129
ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130
ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131
ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132
ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133
ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134
ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135
ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136
ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137
ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138
ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139
port_init_speed_1.BCM8885X=100000
port_init_speed_2.BCM8885X=100000

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@ -1,36 +1 @@
phy set 3 reg=0xd134 data=-8 lane=0
phy set 3 reg=0xd135 data=132 lane=0
phy set 3 reg=0xd136 data=-8 lane=0
phy set 3 reg=0xd137 data=0 lane=0
phy set 3 reg=0xd138 data=0 lane=0
phy set 3 reg=0xd133 data=0x1802 lane=0
phy set 3 reg=0xd134 data=-8 lane=1
phy set 3 reg=0xd135 data=132 lane=1
phy set 3 reg=0xd136 data=-12 lane=1
phy set 3 reg=0xd137 data=0 lane=1
phy set 3 reg=0xd138 data=0 lane=1
phy set 3 reg=0xd133 data=0x1800 lane=1
phy set 3 reg=0xd134 data=-8 lane=7
phy set 3 reg=0xd135 data=132 lane=7
phy set 3 reg=0xd136 data=-8 lane=7
phy set 3 reg=0xd137 data=0 lane=7
phy set 3 reg=0xd138 data=0 lane=7
phy set 3 reg=0xd133 data=0x1804 lane=7
phy set 6 reg=0xd134 data=-8 lane=1
phy set 6 reg=0xd135 data=132 lane=1
phy set 6 reg=0xd136 data=-8 lane=1
phy set 6 reg=0xd137 data=0 lane=1
phy set 6 reg=0xd138 data=0 lane=1
phy set 6 reg=0xd133 data=0x1802 lane=1
phy set 8 reg=0xd134 data=-8 lane=1
phy set 8 reg=0xd135 data=132 lane=1
phy set 8 reg=0xd136 data=-8 lane=1
phy set 8 reg=0xd137 data=0 lane=1
phy set 8 reg=0xd138 data=0 lane=1
phy set 8 reg=0xd133 data=0x1802 lane=1
mod ETPPC_MAP_FWD_QOS_DP_TO_TYPE_FWD 0 128 TYPE_FWD_KEEP_ECN_BITS=1

View File

@ -8,7 +8,7 @@ dma_desc_aggregator_chain_length_max.BCM8885X=1000
dma_desc_aggregator_enable_specific_MDB_LPM.BCM8885X=1
dma_desc_aggregator_timeout_usec.BCM8885X=1000
dport_map_direct.BCM8885X=1
sai_postinit_cmd_file=/usr/share/sonic/hwsku/sai_postinit_cmd.soc
dtm_flow_mapping_mode_region_64.BCM8885X=3
dtm_flow_mapping_mode_region_65.BCM8885X=3
dtm_flow_mapping_mode_region_66.BCM8885X=3
@ -1551,12 +1551,50 @@ ucode_port_15.BCM8885X=CGE6:core_0.15
ucode_port_16.BCM8885X=CGE4:core_0.16
ucode_port_17.BCM8885X=CGE2:core_0.17
ucode_port_18.BCM8885X=CGE0:core_0.18
ucode_port_19.BCM8885X=RCY0:core_0.19
ucode_port_20.BCM8885X=RCY1:core_1.20
ucode_port_21.BCM8885X=OLP:core_1.21
ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100
ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101
ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102
ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103
ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104
ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105
ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106
ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107
ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108
ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109
ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110
ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111
ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112
ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113
ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114
ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115
ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116
ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117
ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118
ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119
ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120
ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121
ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122
ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123
ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124
ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125
ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126
ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127
ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128
ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129
ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130
ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131
ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132
ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133
ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134
ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135
ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136
ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137
ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138
ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139
port_init_speed_1.BCM8885X=100000
port_init_speed_2.BCM8885X=100000

View File

@ -1,6 +1 @@
phy set 8 reg=0xd134 data=-8 lane=1
phy set 8 reg=0xd135 data=132 lane=1
phy set 8 reg=0xd136 data=-8 lane=1
phy set 8 reg=0xd137 data=0 lane=1
phy set 8 reg=0xd138 data=0 lane=1
phy set 8 reg=0xd133 data=0x1802 lane=1
mod ETPPC_MAP_FWD_QOS_DP_TO_TYPE_FWD 0 128 TYPE_FWD_KEEP_ECN_BITS=1

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@ -1551,13 +1551,50 @@ ucode_port_15.BCM8885X=CDGE3:core_0.15
ucode_port_16.BCM8885X=CDGE2:core_0.16
ucode_port_17.BCM8885X=CDGE1:core_0.17
ucode_port_18.BCM8885X=CDGE0:core_0.18
ucode_port_19.BCM8885X=RCY0:core_0.19
ucode_port_20.BCM8885X=RCY1:core_1.20
ucode_port_21.BCM8885X=OLP:core_1.21
ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100
ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101
ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102
ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103
ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104
ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105
ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106
ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107
ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108
ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109
ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110
ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111
ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112
ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113
ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114
ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115
ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116
ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117
ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118
ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119
ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120
ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121
ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122
ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123
ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124
ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125
ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126
ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127
ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128
ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129
ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130
ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131
ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132
ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133
ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134
ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135
ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136
ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137
ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138
ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139
serdes_lane_config_dfe_1.BCM8885X=on
serdes_lane_config_dfe_2.BCM8885X=on

View File

@ -35,3 +35,5 @@ phy set 17 reg=0xd136 data=-16 lane=2
phy set 17 reg=0xd137 data=0 lane=2
phy set 17 reg=0xd138 data=0 lane=2
phy set 17 reg=0xd133 data=0x1804 lane=2
mod ETPPC_MAP_FWD_QOS_DP_TO_TYPE_FWD 0 128 TYPE_FWD_KEEP_ECN_BITS=1

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@ -1551,13 +1551,50 @@ ucode_port_15.BCM8885X=CDGE3:core_0.15
ucode_port_16.BCM8885X=CDGE2:core_0.16
ucode_port_17.BCM8885X=CDGE1:core_0.17
ucode_port_18.BCM8885X=CDGE0:core_0.18
ucode_port_19.BCM8885X=RCY0:core_0.19
ucode_port_20.BCM8885X=RCY1:core_1.20
ucode_port_21.BCM8885X=OLP:core_1.21
ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100
ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101
ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102
ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103
ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104
ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105
ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106
ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107
ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108
ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109
ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110
ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111
ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112
ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113
ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114
ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115
ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116
ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117
ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118
ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119
ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120
ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121
ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122
ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123
ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124
ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125
ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126
ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127
ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128
ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129
ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130
ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131
ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132
ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133
ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134
ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135
ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136
ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137
ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138
ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139
serdes_lane_config_dfe_1.BCM8885X=on
serdes_lane_config_dfe_2.BCM8885X=on

View File

@ -12,3 +12,5 @@ phy set 8 reg=0xd136 data=-8 lane=1
phy set 8 reg=0xd137 data=0 lane=1
phy set 8 reg=0xd138 data=0 lane=1
phy set 8 reg=0xd133 data=0x1802 lane=1
mod ETPPC_MAP_FWD_QOS_DP_TO_TYPE_FWD 0 128 TYPE_FWD_KEEP_ECN_BITS=1