diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers.json.j2 b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers.json.j2
new file mode 100644
index 0000000000..0b1cb2c541
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers.json.j2
@@ -0,0 +1,2 @@
+{%- set default_topo = 't1' %}
+{%- include 'buffers_config.j2' %}
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t0.j2 b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t0.j2
new file mode 100644
index 0000000000..77747f6403
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t0.j2
@@ -0,0 +1,20 @@
+
+{%- set default_cable = '40m' %}
+
+{%- macro generate_buffer_pool_and_profiles() %}
+    "BUFFER_POOL": {
+    },
+    "BUFFER_PROFILE": {
+    },
+{%- endmacro %}
+
+{%- macro generate_pg_profils(port_names_active) %}
+    "BUFFER_PG": {
+    },
+{%- endmacro %}
+
+{% macro generate_queue_buffers(port_names_active) %}
+    "BUFFER_QUEUE": {
+    }
+{% endmacro %}
+
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t1.j2 b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t1.j2
new file mode 100644
index 0000000000..77747f6403
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/buffers_defaults_t1.j2
@@ -0,0 +1,20 @@
+
+{%- set default_cable = '40m' %}
+
+{%- macro generate_buffer_pool_and_profiles() %}
+    "BUFFER_POOL": {
+    },
+    "BUFFER_PROFILE": {
+    },
+{%- endmacro %}
+
+{%- macro generate_pg_profils(port_names_active) %}
+    "BUFFER_PG": {
+    },
+{%- endmacro %}
+
+{% macro generate_queue_buffers(port_names_active) %}
+    "BUFFER_QUEUE": {
+    }
+{% endmacro %}
+
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/custom_led.bin b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/custom_led.bin
new file mode 100755
index 0000000000..3ee9545e28
Binary files /dev/null and b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/custom_led.bin differ
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/linkscan_led_fw.bin b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/linkscan_led_fw.bin
new file mode 100755
index 0000000000..c2fa94a2d8
Binary files /dev/null and b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/linkscan_led_fw.bin differ
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/port_config.ini b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/port_config.ini
new file mode 100644
index 0000000000..d7d83ae21e
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/port_config.ini
@@ -0,0 +1,35 @@
+# name          lanes               alias           index  speed
+Ethernet0       33,34,35,36         hundredGigE1/1   1     100000
+Ethernet8       41,42,43,44         hundredGigE1/2   2     100000
+Ethernet16      49,50,51,52         hundredGigE1/3   3     100000
+Ethernet24      57,58,59,60         hundredGigE1/4   4     100000
+Ethernet32      65,66,67,68         hundredGigE1/5   5     100000
+Ethernet40      73,74,75,76         hundredGigE1/6   6     100000
+Ethernet48      81,82,83,84         hundredGigE1/7   7     100000
+Ethernet56      89,90,91,92         hundredGigE1/8   8     100000
+Ethernet64      1,2,3,4             hundredGigE1/9   9     100000
+Ethernet72      9,10,11,12          hundredGigE1/10  10    100000
+Ethernet80      17,18,19,20         hundredGigE1/11  11    100000
+Ethernet88      25,26,27,28         hundredGigE1/12  12    100000
+Ethernet96      97,98,99,100   	    hundredGigE1/13  13    100000
+Ethernet104     105,106,107,108     hundredGigE1/14  14    100000
+Ethernet112     113,114,115,116     hundredGigE1/15  15    100000
+Ethernet120     121,122,123,124     hundredGigE1/16  16    100000
+Ethernet128     129,130,131,132     hundredGigE1/17  17    100000
+Ethernet136     137,138,139,140     hundredGigE1/18  18    100000
+Ethernet144     145,146,147,148     hundredGigE1/19  19    100000
+Ethernet152     153,154,155,156     hundredGigE1/20  20    100000
+Ethernet160     225,226,227,228     hundredGigE1/21  21    100000
+Ethernet168     233,234,235,236     hundredGigE1/22  22    100000
+Ethernet176     241,242,243,244     hundredGigE1/23  23    100000
+Ethernet184     249,250,251,252     hundredGigE1/24  24    100000
+Ethernet192     161,162,163,164     hundredGigE1/25  25    100000
+Ethernet200     169,170,171,172     hundredGigE1/26  26    100000
+Ethernet208     177,178,179,180     hundredGigE1/27  27    100000
+Ethernet216     185,186,187,188     hundredGigE1/28  28    100000
+Ethernet224     193,194,195,196     hundredGigE1/29  29    100000
+Ethernet232     201,202,203,204     hundredGigE1/30  30    100000
+Ethernet240     209,210,211,212     hundredGigE1/31  31    100000
+Ethernet248     217,218,219,220     hundredGigE1/32  32    100000
+Ethernet256     257                 tenGigE1/33      33    10000
+Ethernet257     258                 tenGigE1/34      34    10000
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2 b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2
new file mode 100644
index 0000000000..f6b7ac977f
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2
@@ -0,0 +1,225 @@
+{%- set PORT_ALL = [] %}
+{%- for port in PORT %}
+    {%- if PORT_ALL.append(port) %}{% endif %}
+{%- endfor %}
+{%- if PORT_ALL | sort_by_port_index %}{% endif %}
+
+{%- set port_names_list_all = [] %}
+{%- for port in PORT_ALL %}
+    {%- if port_names_list_all.append(port) %}{% endif %}
+{%- endfor %}
+{%- set port_names_all = port_names_list_all | join(',') -%}
+
+
+{%- set PORT_ACTIVE = [] %}
+{%- if DEVICE_NEIGHBOR is not defined %}
+    {%- set PORT_ACTIVE = PORT_ALL %}
+{%- else %}
+    {%- for port in DEVICE_NEIGHBOR.keys() %}
+        {%- if PORT_ACTIVE.append(port) %}{%- endif %}
+    {%- endfor %}
+{%- endif %}
+{%- if PORT_ACTIVE | sort_by_port_index %}{% endif %}
+
+{%- set port_names_list_active = [] %}
+{%- for port in PORT_ACTIVE %}
+    {%- if port_names_list_active.append(port) %}{%- endif %}
+{%- endfor %}
+{%- set port_names_active = port_names_list_active | join(',') -%}
+
+
+{%- set pfc_to_pg_map_supported_asics = ['mellanox', 'barefoot', 'marvell'] -%}
+
+
+{
+{% if generate_tc_to_pg_map is defined %}
+    {{- generate_tc_to_pg_map() }}
+{% else %}
+    "TC_TO_PRIORITY_GROUP_MAP": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "0",
+            "2": "0",
+            "3": "0",
+            "4": "0",
+            "5": "0",
+            "6": "0",
+            "7": "7"
+        }
+    },
+{% endif %}
+    "MAP_PFC_PRIORITY_TO_QUEUE": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "1",
+            "2": "2",
+            "3": "3",
+            "4": "4",
+            "5": "5",
+            "6": "6",
+            "7": "7"
+        }
+    },
+    "TC_TO_QUEUE_MAP": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "1",
+            "2": "2",
+            "3": "3",
+            "4": "4",
+            "5": "5",
+            "6": "6",
+            "7": "7"
+        }
+    },
+    "DSCP_TO_TC_MAP": {
+        "DEFAULT": {
+            "0" : "0",
+            "1" : "0",
+            "2" : "0",
+            "3" : "0",
+            "4" : "0",
+            "5" : "0",
+            "6" : "0",
+            "7" : "0",
+            "8" : "0",
+            "9" : "0",
+            "10": "0",
+            "11": "0",
+            "12": "0",
+            "13": "0",
+            "14": "0",
+            "15": "0",
+            "16": "0",
+            "17": "0",
+            "18": "0",
+            "19": "0",
+            "20": "0",
+            "21": "0",
+            "22": "0",
+            "23": "0",
+            "24": "0",
+            "25": "0",
+            "26": "0",
+            "27": "0",
+            "28": "0",
+            "29": "0",
+            "30": "0",
+            "31": "0",
+            "32": "0",
+            "33": "0",
+            "34": "0",
+            "35": "0",
+            "36": "0",
+            "37": "0",
+            "38": "0",
+            "39": "0",
+            "40": "0",
+            "41": "0",
+            "42": "0",
+            "43": "0",
+            "44": "0",
+            "45": "0",
+            "46": "0",
+            "47": "0",
+            "48": "0",
+            "49": "0",
+            "50": "0",
+            "51": "0",
+            "52": "0",
+            "53": "0",
+            "54": "0",
+            "55": "0",
+            "56": "0",
+            "57": "0",
+            "58": "0",
+            "59": "0",
+            "60": "0",
+            "61": "0",
+            "62": "0",
+            "63": "0"
+        }
+    },
+    "SCHEDULER": {
+        "scheduler.0": {
+            "type"  : "DWRR",
+            "weight": "1"
+        },
+        "scheduler.1": {
+            "type"  : "DWRR",
+            "weight": "2"
+        },
+        "scheduler.2": {
+            "type"  : "DWRR",
+            "weight": "3"
+        },
+        "scheduler.3": {
+            "type"  : "DWRR",
+            "weight": "4"
+        },
+        "scheduler.4": {
+            "type"  : "DWRR",
+            "weight": "5"
+        },
+        "scheduler.5": {
+            "type"  : "DWRR",
+            "weight": "10"
+        },
+        "scheduler.6": {
+            "type"  : "DWRR",
+            "weight": "25"
+        },
+        "scheduler.7": {
+            "type"  : "STRICT"
+        }
+    },
+    "PORT_QOS_MAP": {
+        "{{ port_names_active }}": {
+            "dscp_to_tc_map"  : "[DSCP_TO_TC_MAP|DEFAULT]",
+            "tc_to_queue_map" : "[TC_TO_QUEUE_MAP|DEFAULT]",
+            "tc_to_pg_map"    : "[TC_TO_PRIORITY_GROUP_MAP|DEFAULT]"
+        }
+    },
+    "QUEUE": {
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|0": {
+            "scheduler"   : "[SCHEDULER|scheduler.0]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|1": {
+            "scheduler"   : "[SCHEDULER|scheduler.1]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|2": {
+            "scheduler": "[SCHEDULER|scheduler.2]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|3": {
+            "scheduler": "[SCHEDULER|scheduler.3]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|4": {
+            "scheduler": "[SCHEDULER|scheduler.4]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|5": {
+            "scheduler": "[SCHEDULER|scheduler.5]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|6": {
+            "scheduler": "[SCHEDULER|scheduler.6]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|7": {
+            "scheduler": "[SCHEDULER|scheduler.7]"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
+    }
+}
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2.pfc.reference b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2.pfc.reference
new file mode 100644
index 0000000000..1756f106cc
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/qos.json.j2.pfc.reference
@@ -0,0 +1,227 @@
+{%- set PORT_ALL = [] %}
+{%- for port in PORT %}
+    {%- if PORT_ALL.append(port) %}{% endif %}
+{%- endfor %}
+{%- if PORT_ALL | sort_by_port_index %}{% endif %}
+
+{%- set port_names_list_all = [] %}
+{%- for port in PORT_ALL %}
+    {%- if port_names_list_all.append(port) %}{% endif %}
+{%- endfor %}
+{%- set port_names_all = port_names_list_all | join(',') -%}
+
+
+{%- set PORT_ACTIVE = [] %}
+{%- if DEVICE_NEIGHBOR is not defined %}
+    {%- set PORT_ACTIVE = PORT_ALL %}
+{%- else %}
+    {%- for port in DEVICE_NEIGHBOR.keys() %}
+        {%- if PORT_ACTIVE.append(port) %}{%- endif %}
+    {%- endfor %}
+{%- endif %}
+{%- if PORT_ACTIVE | sort_by_port_index %}{% endif %}
+
+{%- set port_names_list_active = [] %}
+{%- for port in PORT_ACTIVE %}
+    {%- if port_names_list_active.append(port) %}{%- endif %}
+{%- endfor %}
+{%- set port_names_active = port_names_list_active | join(',') -%}
+
+
+{%- set pfc_to_pg_map_supported_asics = ['mellanox', 'barefoot', 'marvell'] -%}
+
+
+{
+{% if generate_tc_to_pg_map is defined %}
+    {{- generate_tc_to_pg_map() }}
+{% else %}
+    "TC_TO_PRIORITY_GROUP_MAP": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "0",
+            "2": "0",
+            "3": "3",
+            "4": "4",
+            "5": "0",
+            "6": "0",
+            "7": "7"
+        }
+    },
+{% endif %}
+    "MAP_PFC_PRIORITY_TO_QUEUE": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "1",
+            "2": "2",
+            "3": "3",
+            "4": "4",
+            "5": "5",
+            "6": "6",
+            "7": "7"
+        }
+    },
+    "TC_TO_QUEUE_MAP": {
+        "DEFAULT": {
+            "0": "0",
+            "1": "1",
+            "2": "2",
+            "3": "3",
+            "4": "4",
+            "5": "5",
+            "6": "6",
+            "7": "7"
+        }
+    },
+    "DSCP_TO_TC_MAP": {
+        "DEFAULT": {
+            "0" : "0",
+            "1" : "0",
+            "2" : "0",
+            "3" : "0",
+            "4" : "0",
+            "5" : "0",
+            "6" : "0",
+            "7" : "0",
+            "8" : "0",
+            "9" : "0",
+            "10": "0",
+            "11": "0",
+            "12": "0",
+            "13": "0",
+            "14": "0",
+            "15": "0",
+            "16": "0",
+            "17": "0",
+            "18": "0",
+            "19": "0",
+            "20": "0",
+            "21": "0",
+            "22": "0",
+            "23": "0",
+            "24": "0",
+            "25": "0",
+            "26": "0",
+            "27": "0",
+            "28": "0",
+            "29": "0",
+            "30": "0",
+            "31": "0",
+            "32": "0",
+            "33": "0",
+            "34": "0",
+            "35": "0",
+            "36": "0",
+            "37": "0",
+            "38": "0",
+            "39": "0",
+            "40": "0",
+            "41": "0",
+            "42": "0",
+            "43": "0",
+            "44": "0",
+            "45": "0",
+            "46": "0",
+            "47": "0",
+            "48": "0",
+            "49": "0",
+            "50": "0",
+            "51": "0",
+            "52": "0",
+            "53": "0",
+            "54": "0",
+            "55": "0",
+            "56": "0",
+            "57": "0",
+            "58": "0",
+            "59": "0",
+            "60": "0",
+            "61": "0",
+            "62": "0",
+            "63": "0"
+        }
+    },
+    "SCHEDULER": {
+        "scheduler.0": {
+            "type"  : "DWRR",
+            "weight": "1"
+        },
+        "scheduler.1": {
+            "type"  : "DWRR",
+            "weight": "2"
+        },
+        "scheduler.2": {
+            "type"  : "DWRR",
+            "weight": "3"
+        },
+        "scheduler.3": {
+            "type"  : "DWRR",
+            "weight": "4"
+        },
+        "scheduler.4": {
+            "type"  : "DWRR",
+            "weight": "5"
+        },
+        "scheduler.5": {
+            "type"  : "DWRR",
+            "weight": "10"
+        },
+        "scheduler.6": {
+            "type"  : "DWRR",
+            "weight": "25"
+        },
+        "scheduler.7": {
+            "type"  : "STRICT"
+        }
+    },
+    "PORT_QOS_MAP": {
+        "{{ port_names_active }}": {
+            "dscp_to_tc_map"  : "[DSCP_TO_TC_MAP|DEFAULT]",
+            "tc_to_queue_map" : "[TC_TO_QUEUE_MAP|DEFAULT]",
+            "pfc_enable"      : "3,4",
+            "pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|DEFAULT]",
+            "tc_to_pg_map"    : "[TC_TO_PRIORITY_GROUP_MAP|DEFAULT]"
+        }
+    },
+    "QUEUE": {
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|0": {
+            "scheduler"   : "[SCHEDULER|scheduler.0]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|1": {
+            "scheduler"   : "[SCHEDULER|scheduler.1]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|2": {
+            "scheduler": "[SCHEDULER|scheduler.2]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|3": {
+            "scheduler": "[SCHEDULER|scheduler.3]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|4": {
+            "scheduler": "[SCHEDULER|scheduler.4]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|5": {
+            "scheduler": "[SCHEDULER|scheduler.5]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|6": {
+            "scheduler": "[SCHEDULER|scheduler.6]"
+        },
+{% endfor %}
+{% for port in PORT_ACTIVE %}
+        "{{ port }}|7": {
+            "scheduler": "[SCHEDULER|scheduler.7]"
+        }{% if not loop.last %},{% endif %}
+{% endfor %}
+    }
+}
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai.profile b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai.profile
new file mode 100644
index 0000000000..1c58f69c7e
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai.profile
@@ -0,0 +1 @@
+SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th3-z9332f-32x100G.config.bcm
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_postinit_cmd.soc b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_postinit_cmd.soc
new file mode 100644
index 0000000000..52793ea014
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_postinit_cmd.soc
@@ -0,0 +1,995 @@
+delay 200
+link off
+counter off
+local port ce0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1EC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1EC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce1
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce2
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce3
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce4
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce5
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce6
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x38
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce7
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce8
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce9
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce10
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce11
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce12
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce13
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x34
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce14
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x34
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x30
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce15
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x30
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x2C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x2C
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce16
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x30
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x30
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce17
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x30
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce18
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x38
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x32
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce19
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x34
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x36
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce20
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+
+delay 10
+local port ce21
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce22
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1EC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce23
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce24
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3A
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce25
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x42
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x38
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce26
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce27
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x3E
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce28
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x3C
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F8
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce29
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce30
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x48
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1EC
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F6
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+
+delay 10
+local port ce31
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.0 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.0 TXFIR_TAP2_COEFF=0x40
+phy $port TXFIR_TAP_CTL3r.0 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.0 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.0 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.0 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.1 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.1 TXFIR_TAP2_COEFF=0x4E
+phy $port TXFIR_TAP_CTL3r.1 TXFIR_TAP3_COEFF=0x1EC
+phy $port TXFIR_TAP_CTL4r.1 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.1 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.1 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.2 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.2 TXFIR_TAP2_COEFF=0x44
+phy $port TXFIR_TAP_CTL3r.2 TXFIR_TAP3_COEFF=0x1F4
+phy $port TXFIR_TAP_CTL4r.2 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.2 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.2 TXFIR_TAP_LOAD=0x1
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP0_COEFF=0
+phy $port TXFIR_TAP_CTL1r.3 TXFIR_TAP1_COEFF=0x1FC
+phy $port TXFIR_TAP_CTL2r.3 TXFIR_TAP2_COEFF=0x46
+phy $port TXFIR_TAP_CTL3r.3 TXFIR_TAP3_COEFF=0x1F0
+phy $port TXFIR_TAP_CTL4r.3 TXFIR_TAP4_COEFF=0
+phy $port TXFIR_TAP_CTL5r.3 TXFIR_TAP5_COEFF=0
+phy $port TXFIR_TAP_CTL0r.3 TXFIR_TAP_LOAD=0x1
+link on
+counter on
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_preinit_cmd.soc b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_preinit_cmd.soc
new file mode 100644
index 0000000000..920cd33016
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/sai_preinit_cmd.soc
@@ -0,0 +1,3 @@
+#Not supported in current SAI version
+m0 load 0 0x0 /usr/share/sonic/hwsku/linkscan_led_fw.bin
+m0 load 0 0x3800 /usr/share/sonic/hwsku/custom_led.bin
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/th3-z9332f-32x100G.config.bcm b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/th3-z9332f-32x100G.config.bcm
new file mode 100644
index 0000000000..c3f472b412
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/th3-z9332f-32x100G.config.bcm
@@ -0,0 +1,519 @@
+core_clock_frequency=1325
+dpr_clock_frequency=1000
+device_clock_frequency=1325
+port_flex_enable=1
+
+#firmware load method, use fast load
+load_firmware=0x2
+
+ccm_dma_enable=0
+ccmdma_intr_enable=0
+mem_cache_enable=0
+phy_enable=0
+phy_null=1
+
+dport_map_enable=1
+
+module_64ports.0=0
+tdma_intr_enable.0=1
+ipv6_lpm_128b_enable.0=1
+stat_if_parity_enable.0=1
+oversubscribe_mode=0
+bcm_tunnel_term_compatible_mode.0=1
+table_dma_enable.0=1
+schan_intr_enable.0=0
+parity_enable.0=1
+tdma_timeout_usec=1000000
+lls_num_l2uc.0=10
+miim_intr_enable.0=0
+table_dma_enable=1
+max_vp_lags.0=0
+tdma_intr_enable=1
+tdma_timeout_usec.0=5000000
+parity_correction.0=1
+mmu_lossless.0=0
+bcm_num_cos=8
+default_cpu_tx_queue=7
+pktdma_poll_mode_channel_bitmap=1
+l3_max_ecmp_mode.0=1
+l3_alpm_enable=2
+l3_alpm_ipv6_128b_bkt_rsvd=1
+l2_mem_entries=40960
+l3_mem_entries=40960
+
+l2xlrn_thread_interval=50000
+l2xlrn_intr_en=0
+
+pbmp_xport_xe=0x1ffffffFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
+
+phy_an_c73=3
+
+portmap_1.0=1:100:4
+portmap_5.0=9:100:4
+portmap_10.0=17:100:4
+portmap_14.0=25:100:4
+
+portmap_20.0=33:100:4
+portmap_24.0=41:100:4
+portmap_29.0=49:100:4
+portmap_33.0=57:100:4
+
+portmap_40.0=65:100:4
+portmap_44.0=73:100:4
+portmap_49.0=81:100:4
+portmap_53.0=89:100:4
+
+portmap_60.0=97:100:4
+portmap_64.0=105:100:4
+portmap_69.0=113:100:4
+portmap_73.0=121:100:4
+
+portmap_80.0=129:100:4
+portmap_84.0=137:100:4
+portmap_89.0=145:100:4
+portmap_93.0=153:100:4
+
+portmap_100.0=161:100:4
+portmap_104.0=169:100:4
+portmap_109.0=177:100:4
+portmap_113.0=185:100:4
+
+portmap_120.0=193:100:4
+portmap_124.0=201:100:4
+portmap_129.0=209:100:4
+portmap_133.0=217:100:4
+
+portmap_140.0=225:100:4
+portmap_144.0=233:100:4
+portmap_149.0=241:100:4
+portmap_153.0=249:100:4
+
+portmap_38.0=257:10:1
+portmap_118.0=258:10:1
+
+dport_map_port_20=1
+dport_map_port_21=2
+dport_map_port_22=3
+dport_map_port_23=4
+dport_map_port_24=5
+dport_map_port_25=6
+dport_map_port_26=7
+dport_map_port_27=8
+dport_map_port_28=9
+dport_map_port_29=10
+dport_map_port_30=11
+dport_map_port_31=12
+dport_map_port_32=13
+dport_map_port_33=14
+dport_map_port_34=15
+dport_map_port_35=16
+dport_map_port_36=17
+dport_map_port_37=18
+dport_map_port_40=19
+dport_map_port_41=20
+dport_map_port_42=21
+dport_map_port_43=22
+dport_map_port_44=23
+dport_map_port_45=24
+dport_map_port_46=25
+dport_map_port_47=26
+dport_map_port_48=27
+dport_map_port_49=28
+dport_map_port_50=29
+dport_map_port_51=30
+dport_map_port_52=31
+dport_map_port_53=32
+dport_map_port_54=33
+dport_map_port_55=34
+dport_map_port_56=35
+dport_map_port_57=36
+dport_map_port_1=37
+dport_map_port_2=38
+dport_map_port_3=39
+dport_map_port_4=40
+dport_map_port_5=41
+dport_map_port_6=42
+dport_map_port_7=43
+dport_map_port_8=44
+dport_map_port_9=45
+dport_map_port_10=46
+dport_map_port_11=47
+dport_map_port_12=48
+dport_map_port_13=49
+dport_map_port_14=50
+dport_map_port_15=51
+dport_map_port_16=52
+dport_map_port_17=53
+dport_map_port_18=54
+dport_map_port_60=55
+dport_map_port_61=56
+dport_map_port_62=57
+dport_map_port_63=58
+dport_map_port_64=59
+dport_map_port_65=60
+dport_map_port_66=61
+dport_map_port_67=62
+dport_map_port_68=63
+dport_map_port_69=64
+dport_map_port_70=65
+dport_map_port_71=66
+dport_map_port_72=67
+dport_map_port_73=68
+dport_map_port_74=69
+dport_map_port_75=70
+dport_map_port_76=71
+dport_map_port_77=72
+dport_map_port_80=73
+dport_map_port_81=74
+dport_map_port_82=75
+dport_map_port_83=76
+dport_map_port_84=77
+dport_map_port_85=78
+dport_map_port_86=79
+dport_map_port_87=80
+dport_map_port_88=81
+dport_map_port_89=82
+dport_map_port_90=83
+dport_map_port_91=84
+dport_map_port_92=85
+dport_map_port_93=86
+dport_map_port_94=87
+dport_map_port_95=88
+dport_map_port_96=89
+dport_map_port_97=90
+dport_map_port_140=91
+dport_map_port_141=92
+dport_map_port_142=93
+dport_map_port_143=94
+dport_map_port_144=95
+dport_map_port_145=96
+dport_map_port_146=97
+dport_map_port_147=98
+dport_map_port_148=99
+dport_map_port_149=100
+dport_map_port_150=101
+dport_map_port_151=102
+dport_map_port_152=103
+dport_map_port_153=104
+dport_map_port_154=105
+dport_map_port_155=106
+dport_map_port_156=107
+dport_map_port_157=108
+dport_map_port_100=109
+dport_map_port_101=110
+dport_map_port_102=111
+dport_map_port_103=112
+dport_map_port_104=113
+dport_map_port_105=114
+dport_map_port_106=115
+dport_map_port_107=116
+dport_map_port_108=117
+dport_map_port_109=118
+dport_map_port_110=119
+dport_map_port_111=120
+dport_map_port_112=121
+dport_map_port_113=122
+dport_map_port_114=123
+dport_map_port_115=124
+dport_map_port_116=125
+dport_map_port_117=126
+dport_map_port_120=127
+dport_map_port_121=128
+dport_map_port_122=129
+dport_map_port_123=130
+dport_map_port_124=131
+dport_map_port_125=132
+dport_map_port_126=133
+dport_map_port_127=134
+dport_map_port_128=135
+dport_map_port_129=136
+dport_map_port_130=137
+dport_map_port_131=138
+dport_map_port_132=139
+dport_map_port_133=140
+dport_map_port_134=141
+dport_map_port_135=142
+dport_map_port_136=143
+dport_map_port_137=144
+dport_map_port_38=145
+dport_map_port_118=146
+
+phy_chain_rx_lane_map_physical{33.0}=0x65732041
+phy_chain_tx_lane_map_physical{33.0}=0x47206531
+phy_chain_rx_lane_map_physical{41.0}=0x07561243
+phy_chain_tx_lane_map_physical{41.0}=0x36207514
+phy_chain_rx_lane_map_physical{49.0}=0x54632071
+phy_chain_tx_lane_map_physical{49.0}=0x06241735
+phy_chain_rx_lane_map_physical{57.0}=0x07561243
+phy_chain_tx_lane_map_physical{57.0}=0x35207614
+phy_chain_rx_lane_map_physical{65.0}=0x45623170
+phy_chain_tx_lane_map_physical{65.0}=0x51260734
+phy_chain_rx_lane_map_physical{73.0}=0x07561243
+phy_chain_tx_lane_map_physical{73.0}=0x37245610
+phy_chain_rx_lane_map_physical{81.0}=0x45632071
+phy_chain_tx_lane_map_physical{81.0}=0x51260734
+phy_chain_rx_lane_map_physical{89.0}=0x07561243
+phy_chain_tx_lane_map_physical{89.0}=0x26437510
+phy_chain_rx_lane_map_physical{1.0}=0x30176524
+phy_chain_tx_lane_map_physical{1.0}=0x20615374
+phy_chain_rx_lane_map_physical{9.0}=0x37562041
+phy_chain_tx_lane_map_physical{9.0}=0x05176432
+phy_chain_rx_lane_map_physical{17.0}=0x43607251
+phy_chain_tx_lane_map_physical{17.0}=0x70261435
+phy_chain_rx_lane_map_physical{25.0}=0x60347125
+phy_chain_tx_lane_map_physical{25.0}=0x46357120
+phy_chain_rx_lane_map_physical{97.0}=0x47601352
+phy_chain_tx_lane_map_physical{97.0}=0x04265137
+phy_chain_rx_lane_map_physical{105.0}=0x73206415
+phy_chain_tx_lane_map_physical{105.0}=0x26374150
+phy_chain_rx_lane_map_physical{113.0}=0x47632051
+phy_chain_tx_lane_map_physical{113.0}=0x03254617
+phy_chain_rx_lane_map_physical{121.0}=0x63027415
+phy_chain_tx_lane_map_physical{121.0}=0x63721045
+phy_chain_rx_lane_map_physical{129.0}=0x30154627
+phy_chain_tx_lane_map_physical{129.0}=0x04735261
+phy_chain_rx_lane_map_physical{137.0}=0x24753061
+phy_chain_tx_lane_map_physical{137.0}=0x37614520
+phy_chain_rx_lane_map_physical{145.0}=0x47601352
+phy_chain_tx_lane_map_physical{145.0}=0x63274510
+phy_chain_rx_lane_map_physical{153.0}=0x07361524
+phy_chain_tx_lane_map_physical{153.0}=0x36527104
+phy_chain_rx_lane_map_physical{225.0}=0x56410273
+phy_chain_tx_lane_map_physical{225.0}=0x10274635
+phy_chain_rx_lane_map_physical{233.0}=0x15740263
+phy_chain_tx_lane_map_physical{233.0}=0x24351607
+phy_chain_rx_lane_map_physical{241.0}=0x74015263
+phy_chain_tx_lane_map_physical{241.0}=0x04152637
+phy_chain_rx_lane_map_physical{249.0}=0x62037514
+phy_chain_tx_lane_map_physical{249.0}=0x72453160
+phy_chain_rx_lane_map_physical{161.0}=0x46510273
+phy_chain_tx_lane_map_physical{161.0}=0x01653724
+phy_chain_rx_lane_map_physical{169.0}=0x25743160
+phy_chain_tx_lane_map_physical{169.0}=0x07216435
+phy_chain_rx_lane_map_physical{177.0}=0x46510273
+phy_chain_tx_lane_map_physical{177.0}=0x01652734
+phy_chain_rx_lane_map_physical{185.0}=0x25743160
+phy_chain_tx_lane_map_physical{185.0}=0x37016425
+phy_chain_rx_lane_map_physical{193.0}=0x46510372
+phy_chain_tx_lane_map_physical{193.0}=0x06153724
+phy_chain_rx_lane_map_physical{201.0}=0x25743160
+phy_chain_tx_lane_map_physical{201.0}=0x36017524
+phy_chain_rx_lane_map_physical{209.0}=0x47601352
+phy_chain_tx_lane_map_physical{209.0}=0x04152736
+phy_chain_rx_lane_map_physical{217.0}=0x26453170
+phy_chain_tx_lane_map_physical{217.0}=0x36027415
+
+serdes_core_rx_polarity_flip_physical{33}=0x29
+serdes_core_tx_polarity_flip_physical{33}=0xfe
+serdes_core_rx_polarity_flip_physical{41}=0xb1
+serdes_core_tx_polarity_flip_physical{41}=0xe8
+serdes_core_rx_polarity_flip_physical{49}=0xca
+serdes_core_tx_polarity_flip_physical{49}=0xb6
+serdes_core_rx_polarity_flip_physical{57}=0x9b
+serdes_core_tx_polarity_flip_physical{57}=0xdc
+serdes_core_rx_polarity_flip_physical{65}=0x17
+serdes_core_tx_polarity_flip_physical{65}=0x86
+serdes_core_rx_polarity_flip_physical{73}=0x9b
+serdes_core_tx_polarity_flip_physical{73}=0x55
+serdes_core_rx_polarity_flip_physical{81}=0xa
+serdes_core_tx_polarity_flip_physical{81}=0x6
+serdes_core_rx_polarity_flip_physical{89}=0x9b
+serdes_core_tx_polarity_flip_physical{89}=0x48
+serdes_core_rx_polarity_flip_physical{1}=0xec
+serdes_core_tx_polarity_flip_physical{1}=0x56
+serdes_core_rx_polarity_flip_physical{9}=0x13
+serdes_core_tx_polarity_flip_physical{9}=0xa6
+serdes_core_rx_polarity_flip_physical{17}=0x5a
+serdes_core_tx_polarity_flip_physical{17}=0xc6
+serdes_core_rx_polarity_flip_physical{25}=0xf
+serdes_core_tx_polarity_flip_physical{25}=0x4e
+serdes_core_rx_polarity_flip_physical{97}=0x17
+serdes_core_tx_polarity_flip_physical{97}=0x2e
+serdes_core_rx_polarity_flip_physical{105}=0xce
+serdes_core_tx_polarity_flip_physical{105}=0x7c
+serdes_core_rx_polarity_flip_physical{113}=0xa
+serdes_core_tx_polarity_flip_physical{113}=0x35
+
+serdes_core_rx_polarity_flip_physical{121}=0xb9
+serdes_core_tx_polarity_flip_physical{121}=0xef
+serdes_core_rx_polarity_flip_physical{129}=0xe8
+serdes_core_tx_polarity_flip_physical{129}=0xac
+serdes_core_rx_polarity_flip_physical{137}=0xcb
+serdes_core_tx_polarity_flip_physical{137}=0x9c
+serdes_core_rx_polarity_flip_physical{145}=0x17
+serdes_core_tx_polarity_flip_physical{145}=0x32
+serdes_core_rx_polarity_flip_physical{153}=0xb9
+serdes_core_tx_polarity_flip_physical{153}=0xaf
+serdes_core_rx_polarity_flip_physical{225}=0xaa
+serdes_core_tx_polarity_flip_physical{225}=0x7
+serdes_core_rx_polarity_flip_physical{233}=0x31
+serdes_core_tx_polarity_flip_physical{233}=0x47
+serdes_core_rx_polarity_flip_physical{241}=0xe8
+serdes_core_tx_polarity_flip_physical{241}=0x9e
+serdes_core_rx_polarity_flip_physical{249}=0xec
+serdes_core_tx_polarity_flip_physical{249}=0x1f
+serdes_core_rx_polarity_flip_physical{161}=0x6a
+serdes_core_tx_polarity_flip_physical{161}=0xd4
+serdes_core_rx_polarity_flip_physical{169}=0x9e
+serdes_core_tx_polarity_flip_physical{169}=0x7b
+serdes_core_rx_polarity_flip_physical{177}=0x6a
+serdes_core_tx_polarity_flip_physical{177}=0xcc
+serdes_core_rx_polarity_flip_physical{185}=0x9e
+serdes_core_tx_polarity_flip_physical{185}=0x58
+serdes_core_rx_polarity_flip_physical{193}=0x6f
+serdes_core_tx_polarity_flip_physical{193}=0x24
+serdes_core_rx_polarity_flip_physical{201}=0x9e
+serdes_core_tx_polarity_flip_physical{201}=0xdf
+serdes_core_rx_polarity_flip_physical{209}=0x17
+serdes_core_tx_polarity_flip_physical{209}=0xe9
+serdes_core_rx_polarity_flip_physical{217}=0xec
+serdes_core_tx_polarity_flip_physical{217}=0x68
+
+serdes_lane_config_media_type_49=copper
+serdes_lane_config_media_type_50=copper
+serdes_lane_config_media_type_51=copper
+serdes_lane_config_media_type_52=copper
+serdes_lane_config_media_type_54=copper
+serdes_lane_config_media_type_55=copper
+serdes_lane_config_media_type_56=copper
+serdes_lane_config_media_type_57=copper
+serdes_lane_config_media_type_53=copper
+serdes_lane_config_media_type_60=copper
+serdes_lane_config_media_type_61=copper
+serdes_lane_config_media_type_62=copper
+serdes_lane_config_media_type_63=copper
+serdes_lane_config_media_type_65=copper
+serdes_lane_config_media_type_66=copper
+serdes_lane_config_media_type_67=copper
+serdes_lane_config_media_type_68=copper
+serdes_lane_config_media_type_64=copper
+serdes_lane_config_media_type_80=copper
+serdes_lane_config_media_type_81=copper
+serdes_lane_config_media_type_82=copper
+serdes_lane_config_media_type_83=copper
+serdes_lane_config_media_type_85=copper
+serdes_lane_config_media_type_86=copper
+serdes_lane_config_media_type_87=copper
+serdes_lane_config_media_type_88=copper
+serdes_lane_config_media_type_84=copper
+serdes_lane_config_media_type_100=copper
+serdes_lane_config_media_type_101=copper
+serdes_lane_config_media_type_102=copper
+serdes_lane_config_media_type_103=copper
+serdes_lane_config_media_type_105=copper
+serdes_lane_config_media_type_106=copper
+serdes_lane_config_media_type_107=copper
+serdes_lane_config_media_type_108=copper
+serdes_lane_config_media_type_104=copper
+serdes_lane_config_media_type_120=copper
+serdes_lane_config_media_type_121=copper
+serdes_lane_config_media_type_122=copper
+serdes_lane_config_media_type_123=copper
+serdes_lane_config_media_type_125=copper
+serdes_lane_config_media_type_126=copper
+serdes_lane_config_media_type_127=copper
+serdes_lane_config_media_type_128=copper
+serdes_lane_config_media_type_124=copper
+serdes_lane_config_media_type_140=copper
+serdes_lane_config_media_type_141=copper
+serdes_lane_config_media_type_142=copper
+serdes_lane_config_media_type_143=copper
+serdes_lane_config_media_type_145=copper
+serdes_lane_config_media_type_146=copper
+serdes_lane_config_media_type_147=copper
+serdes_lane_config_media_type_148=copper
+serdes_lane_config_media_type_144=copper
+serdes_lane_config_media_type_40=copper
+serdes_lane_config_media_type_41=copper
+serdes_lane_config_media_type_42=copper
+serdes_lane_config_media_type_43=copper
+serdes_lane_config_media_type_45=copper
+serdes_lane_config_media_type_46=copper
+serdes_lane_config_media_type_47=copper
+serdes_lane_config_media_type_48=copper
+serdes_lane_config_media_type_44=copper
+serdes_lane_config_media_type_69=copper
+serdes_lane_config_media_type_70=copper
+serdes_lane_config_media_type_71=copper
+serdes_lane_config_media_type_72=copper
+serdes_lane_config_media_type_74=copper
+serdes_lane_config_media_type_75=copper
+serdes_lane_config_media_type_76=copper
+serdes_lane_config_media_type_77=copper
+serdes_lane_config_media_type_73=copper
+serdes_lane_config_media_type_1=copper
+serdes_lane_config_media_type_2=copper
+serdes_lane_config_media_type_3=copper
+serdes_lane_config_media_type_4=copper
+serdes_lane_config_media_type_6=copper
+serdes_lane_config_media_type_7=copper
+serdes_lane_config_media_type_8=copper
+serdes_lane_config_media_type_9=copper
+serdes_lane_config_media_type_5=copper
+serdes_lane_config_media_type_29=copper
+serdes_lane_config_media_type_30=copper
+serdes_lane_config_media_type_31=copper
+serdes_lane_config_media_type_32=copper
+serdes_lane_config_media_type_34=copper
+serdes_lane_config_media_type_35=copper
+serdes_lane_config_media_type_36=copper
+serdes_lane_config_media_type_37=copper
+serdes_lane_config_media_type_33=copper
+serdes_lane_config_media_type_89=copper
+serdes_lane_config_media_type_90=copper
+serdes_lane_config_media_type_91=copper
+serdes_lane_config_media_type_92=copper
+serdes_lane_config_media_type_94=copper
+serdes_lane_config_media_type_95=copper
+serdes_lane_config_media_type_96=copper
+serdes_lane_config_media_type_97=copper
+serdes_lane_config_media_type_93=copper
+serdes_lane_config_media_type_109=copper
+serdes_lane_config_media_type_110=copper
+serdes_lane_config_media_type_111=copper
+serdes_lane_config_media_type_112=copper
+serdes_lane_config_media_type_114=copper
+serdes_lane_config_media_type_115=copper
+serdes_lane_config_media_type_116=copper
+serdes_lane_config_media_type_117=copper
+serdes_lane_config_media_type_113=copper
+serdes_lane_config_media_type_129=copper
+serdes_lane_config_media_type_130=copper
+serdes_lane_config_media_type_131=copper
+serdes_lane_config_media_type_132=copper
+serdes_lane_config_media_type_134=copper
+serdes_lane_config_media_type_135=copper
+serdes_lane_config_media_type_136=copper
+serdes_lane_config_media_type_137=copper
+serdes_lane_config_media_type_133=copper
+serdes_lane_config_media_type_149=copper
+serdes_lane_config_media_type_150=copper
+serdes_lane_config_media_type_151=copper
+serdes_lane_config_media_type_152=copper
+serdes_lane_config_media_type_154=copper
+serdes_lane_config_media_type_155=copper
+serdes_lane_config_media_type_156=copper
+serdes_lane_config_media_type_157=copper
+serdes_lane_config_media_type_153=copper
+serdes_lane_config_media_type_10=copper
+serdes_lane_config_media_type_11=copper
+serdes_lane_config_media_type_12=copper
+serdes_lane_config_media_type_13=copper
+serdes_lane_config_media_type_15=copper
+serdes_lane_config_media_type_16=copper
+serdes_lane_config_media_type_17=copper
+serdes_lane_config_media_type_18=copper
+serdes_lane_config_media_type_14=copper
+serdes_lane_config_media_type_20=copper
+serdes_lane_config_media_type_21=copper
+serdes_lane_config_media_type_22=copper
+serdes_lane_config_media_type_23=copper
+serdes_lane_config_media_type_25=copper
+serdes_lane_config_media_type_26=copper
+serdes_lane_config_media_type_27=copper
+serdes_lane_config_media_type_28=copper
+serdes_lane_config_media_type_24=copper
+
+#sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc
+sai_postinit_cmd_file=/usr/share/sonic/hwsku/sai_postinit_cmd.soc
+
diff --git a/device/dell/x86_64-dellemc_z9332f_d1508-r0/pmon_daemon_control.json b/device/dell/x86_64-dellemc_z9332f_d1508-r0/pmon_daemon_control.json
new file mode 100644
index 0000000000..94592fa8ce
--- /dev/null
+++ b/device/dell/x86_64-dellemc_z9332f_d1508-r0/pmon_daemon_control.json
@@ -0,0 +1,3 @@
+{
+    "skip_ledd": true
+}