50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
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From 6cb8f4e432f8209a3775877d690a979a2e786afc Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Mon, 27 Feb 2023 18:56:09 +0000
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Subject: [PATCH backport 5.10 3/3] platform: mellanox: Add new attributes
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Add two new attributes:
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"lid_open" - to indicate system intrusion detection.
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"reset_long_pwr_pb" - to indicate that system has been reset due to
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long press of power button.
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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Reviewed-by: Michael Shych <michaelsh@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index 42fd7e4e0..4eb327720 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -4067,6 +4067,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(1),
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.mode = 0444,
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},
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+ {
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+ .label = "lid_open",
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+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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+ .mask = GENMASK(7, 0) & ~BIT(2),
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+ .mode = 0444,
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+ },
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{
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.label = "clk_brd1_boot_fail",
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.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
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@@ -4706,6 +4712,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(6),
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.mode = 0444,
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},
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+ {
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+ .label = "reset_long_pwr_pb",
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+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
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+ .mask = GENMASK(7, 0) & ~BIT(7),
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+ .mode = 0444,
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+ },
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{
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.label = "pwr_cycle",
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.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
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--
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2.20.1
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