sonic-buildimage/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/pg_profile_lookup.ini

#  PG lossless profiles.
# speed cable  size   xon    xoff  threshold
  10000    5m 41984  19456  22528          0
  25000    5m 41984  19456  22528          0
  40000    5m 41984  19456  22528          0
  50000    5m 41984  19456  22528          0
 100000    5m 43008  19456  23552          0
  10000   40m 41984  19456  22528          0
  25000   40m 44032  19456  24576          0
  40000   40m 45056  19456  25600          0
  50000   40m 45056  19456  25600          0
 100000   40m 49152  19456  29696          0
  10000  300m 47104  19456  27648          0
  25000  300m 56320  19456  36864          0
  40000  300m 64512  19456  45056          0
  50000  300m 69632  19456  50176          0
 100000  300m 98304  19456  78848          0
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194) This is to backport the #4886 to 201911 Calculate pool size in t1 as 24 * downlink port + 8 * uplink port - Take both port and peer MTU into account when calculating headroom - Worst case factor is decreased to 50% - Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports - Mellanox-SN2700 (C32) - t0: 16 * 100G/5m + 16 * 100G/40m - t1: 16 * 100G/40m + 16 * 100G/300m Signed-off-by: Stephen Sun <stephens@nvidia.com> 2020-08-15 09:52:28 -05:00			`# PG lossless profiles.`
			`# speed cable size xon xoff threshold`
			`10000 5m 41984 19456 22528 0`
			`25000 5m 41984 19456 22528 0`
			`40000 5m 41984 19456 22528 0`
			`50000 5m 41984 19456 22528 0`
			`100000 5m 43008 19456 23552 0`
			`10000 40m 41984 19456 22528 0`
			`25000 40m 44032 19456 24576 0`
			`40000 40m 45056 19456 25600 0`
			`50000 40m 45056 19456 25600 0`
			`100000 40m 49152 19456 29696 0`
			`10000 300m 47104 19456 27648 0`
			`25000 300m 56320 19456 36864 0`
			`40000 300m 64512 19456 45056 0`
			`50000 300m 69632 19456 50176 0`
			`100000 300m 98304 19456 78848 0`