467 lines
14 KiB
C
467 lines
14 KiB
C
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/*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to
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* you under the terms of the GNU General Public License version 2 (the
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* "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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* with the following added to such license:
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*
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* As a special exception, the copyright holders of this software give
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* you permission to link this software with independent modules, and to
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* copy and distribute the resulting executable under terms of your
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* choice, provided that you also meet, for each linked independent
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* module, the terms and conditions of the license of that module. An
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* independent module is a module which is not derived from this
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* software. The special exception does not apply to any modifications
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* of the software.
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*/
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/*
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* $Id: $
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* $Copyright: (c) 2014 Broadcom Corp.
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* All Rights Reserved.$
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*
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*/
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#include <shbde_iproc.h>
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#include <shbde_mdio.h>
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#include <shbde_pci.h>
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/* PAXB register offsets within PCI BAR0 window */
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#define BAR0_PAXB_ENDIANESS 0x2030
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#define BAR0_PAXB_PCIE_EP_AXI_CONFIG 0x2104
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#define BAR0_PAXB_CONFIG_IND_ADDR 0x2120
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#define BAR0_PAXB_CONFIG_IND_DATA 0x2124
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#define BAR0_PAXB_IMAP0_0 (0x2c00)
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#define BAR0_PAXB_IMAP0_1 (0x2c04)
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#define BAR0_PAXB_IMAP0_2 (0x2c08)
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#define BAR0_PAXB_IMAP0_7 (0x2c1c)
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#define BAR0_PAXB_OARR_FUNC0_MSI_PAGE 0x2d34
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#define BAR0_PAXB_OARR_2 0x2d60
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#define BAR0_PAXB_OARR_2_UPPER 0x2d64
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#define BAR0_DMU_PCU_PCIE_SLAVE_RESET_MODE 0x7024
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/* Force byte pointer for offset adjustments */
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#define ROFFS(_ptr, _offset) ((unsigned char*)(_ptr) + (_offset))
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#define PAXB_CONFIG_IND_ADDRr_PROTOCOL_LAYERf_SHFT 11
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#define PAXB_CONFIG_IND_ADDRr_PROTOCOL_LAYERf_MASK 0x3
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#define PAXB_CONFIG_IND_ADDRr_ADDRESSf_SHFT 0
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#define PAXB_CONFIG_IND_ADDRr_ADDRESSf_MASK 0x7ff
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/* Register value set/get by field */
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#define REG_FIELD_SET(_r, _f, _r_val, _f_val) \
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_r_val = ((_r_val) & ~(_r##_##_f##_MASK << _r##_##_f##_SHFT)) | \
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(((_f_val) & _r##_##_f##_MASK) << _r##_##_f##_SHFT)
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#define REG_FIELD_GET(_r, _f, _r_val) \
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(((_r_val) >> _r##_##_f##_SHFT) & _r##_##_f##_MASK)
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/* PCIe capabilities definition */
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#ifndef PCI_EXP_LNKSTA
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#define PCI_EXP_LNKSTA 0x12
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#endif
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/* Current Link Speed 5.0GT/s */
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#ifndef PCI_EXP_LNKSTA_CLS_5_0GB
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#define PCI_EXP_LNKSTA_CLS_5_0GB 2
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#endif
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#ifndef PCI_EXP_LNKSTA2
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#define PCI_EXP_LNKSTA2 0x32
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#endif
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/* Current Deemphasis Level -3.5 dB */
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#ifndef PCI_EXP_LNKSTA2_CDL_3_5DB
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#define PCI_EXP_LNKSTA2_CDL_3_5DB 0x1
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#endif
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static unsigned int
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iproc32_read(shbde_hal_t *shbde, void *addr)
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{
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if (!shbde || !shbde->io32_read) {
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return 0;
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}
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return shbde->io32_read(addr);
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}
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static void
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iproc32_write(shbde_hal_t *shbde, void *addr, unsigned int data)
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{
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if (!shbde || !shbde->io32_write) {
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return;
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}
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shbde->io32_write(addr, data);
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}
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static void
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wait_usec(shbde_hal_t *shbde, int usec)
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{
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if (shbde && shbde->usleep) {
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shbde->usleep(usec);
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} else {
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int idx;
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volatile int count;
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for (idx = 0; idx < usec; idx++) {
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for (count = 0; count < 100; count++);
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}
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}
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}
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/*
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* Function:
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* shbde_iproc_config_init
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* Purpose:
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* Initialize iProc configuration parameters
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* Parameters:
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* icfg - pointer to empty iProc configuration structure
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* Returns:
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* -1 if error, otherwise 0
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*/
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int
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shbde_iproc_config_init(shbde_iproc_config_t *icfg,
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unsigned int dev_id, unsigned int dev_rev)
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{
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if (!icfg) {
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return -1;
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}
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/* Save device ID and revision */
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icfg->dev_id = dev_id;
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icfg->dev_rev = dev_rev;
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/* Check device families first */
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switch (icfg->dev_id & 0xfff0) {
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case 0x8400: /* Greyhound Lite */
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case 0x8410: /* Greyhound */
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case 0x8420: /* Bloodhound */
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case 0x8450: /* Elkhound */
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case 0xb060: /* Ranger2(Greyhound) */
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case 0x8360: /* Greyhound 53365 & 53369 */
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case 0xb260: /* saber2 */
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case 0xb460: /* saber2+ */
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case 0xb170: /* Hurricane3-MG */
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case 0x8570: /* Greyhound2 */
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case 0xb070: /* Greyhound2(emulation) */
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case 0x8580: /* Greyhound2(emulation) */
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case 0xb230: /* Dagger2 */
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icfg->iproc_ver = 7;
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icfg->dma_hi_bits = 0x2;
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break;
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case 0xb560: /* Apache */
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case 0xb760: /* Maverick */
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icfg->iproc_ver = 0xB;
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break;
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case 0xb160: /* Hurricane3 */
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case 0x8440: /* Wolfhound2 */
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case 0x8430: /* Foxhound2 */
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icfg->iproc_ver = 10;
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icfg->dma_hi_bits = 0x2;
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break;
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default:
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break;
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}
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/* Check for exceptions */
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switch (icfg->dev_id) {
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case 0xb069:
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case 0xb068:
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icfg->iproc_ver = 0xB; /*Ranger2+ Apache Family */
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icfg->dma_hi_bits = 0;
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break;
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case 0xb168: /* Ranger3+ */
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case 0xb169:
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icfg->iproc_ver = 0;
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icfg->dma_hi_bits = 0;
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break;
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default:
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break;
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}
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/* Check for PCIe PHY address that needs PCIe preemphasis and
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* assign the MDIO base address
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*/
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switch (icfg->dev_id & 0xfff0) {
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case 0xb150: /* Hurricane2 */
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case 0x8340: /* Wolfhound */
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case 0x8330: /* Foxhound */
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case 0x8390: /* Dearhound */
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icfg->mdio_base_addr = 0x18032000;
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icfg->pcie_phy_addr = 0x2;
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break;
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case 0xb340: /* Helilx4 */
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case 0xb540: /* FireScout */
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case 0xb040: /* Spiral, Ranger */
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icfg->mdio_base_addr = 0x18032000;
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icfg->pcie_phy_addr = 0x5;
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icfg->adjust_pcie_preemphasis = 1;
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break;
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case 0xa450: /* Katana2 */
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case 0xb240:
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case 0xb450:
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icfg->mdio_base_addr = 0x18032000;
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icfg->pcie_phy_addr = 0x5;
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icfg->adjust_pcie_preemphasis = 1;
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break;
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default:
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break;
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}
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/* Check for exceptions */
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switch (icfg->dev_id) {
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default:
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break;
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}
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return 0;
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}
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/*
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* Function:
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* shbde_iproc_paxb_init
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* Purpose:
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* Initialize iProc PCI-AXI bridge for CMIC access
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* iproc_regs - memory mapped iProc registers in PCI BAR
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* icfg - iProc configuration parameters
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* Returns:
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* -1 if error, otherwise 0
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*/
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int
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shbde_iproc_paxb_init(shbde_hal_t *shbde, void *iproc_regs,
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shbde_iproc_config_t *icfg)
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{
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void *reg;
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unsigned int data;
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int pci_num;
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if (!iproc_regs || !icfg) {
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return -1;
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}
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/*
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* The following code attempts to auto-detect the correct
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* iProc PCI endianess configuration by reading a well-known
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* register (the endianess configuration register itself).
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* Note that the PCI endianess may be different for different
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* big endian host processors.
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*/
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reg = ROFFS(iproc_regs, BAR0_PAXB_ENDIANESS);
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/* Select big endian */
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iproc32_write(shbde, reg, 0x01010101);
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/* Check if endianess register itself is correct endian */
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if (iproc32_read(shbde, reg) != 1) {
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/* If not, then assume little endian */
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iproc32_write(shbde, reg, 0x0);
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}
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/* Select which PCI core to use */
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pci_num = 0;
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reg = ROFFS(iproc_regs, BAR0_PAXB_IMAP0_2);
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data = iproc32_read(shbde, reg);
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if (data & 0x1000) {
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/* PAXB_1 is mapped to sub-window 2 */
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pci_num = 1;
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}
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/* Default DMA mapping if uninitialized */
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if (icfg->dma_hi_bits == 0) {
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icfg->dma_hi_bits = 0x1;
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if (pci_num == 1) {
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icfg->dma_hi_bits = 0x2;
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}
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}
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/* Enable iProc DMA to external host memory */
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reg = ROFFS(iproc_regs, BAR0_PAXB_PCIE_EP_AXI_CONFIG);
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iproc32_write(shbde, reg, 0x0);
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if(icfg->cmic_ver < 4) { /* Non-CMICX */
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reg = ROFFS(iproc_regs, BAR0_PAXB_OARR_2);
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iproc32_write(shbde, reg, 0x1);
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reg = ROFFS(iproc_regs, BAR0_PAXB_OARR_2_UPPER);
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iproc32_write(shbde, reg, icfg->dma_hi_bits);
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/* Configure MSI interrupt page */
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if (icfg->use_msi) {
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reg = ROFFS(iproc_regs, BAR0_PAXB_OARR_FUNC0_MSI_PAGE);
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data = iproc32_read(shbde, reg);
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iproc32_write(shbde, reg, data | 0x1);
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}
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}
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return pci_num;
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}
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/*
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* Function:
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* shbde_iproc_pci_read
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* Purpose:
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* Read iProc register through PCI BAR 0
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* iproc_regs - memory mapped iProc registers in PCI BAR
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* addr - iProc register address in AXI memory space
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* Returns:
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* Register value
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*/
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unsigned int
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shbde_iproc_pci_read(shbde_hal_t *shbde, void *iproc_regs,
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unsigned int addr)
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{
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unsigned int subwin_base;
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void *reg;
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shbde_iproc_config_t *icfg = &shbde->icfg;
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if (!iproc_regs) {
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return -1;
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}
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/* Sub-window size is 0x1000 (4K) */
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subwin_base = (addr & ~0xfff);
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if((icfg->cmic_ver >= 4) && (subwin_base == 0x18013000)) {
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/* Route the INTC block access through IMAP0_6 */
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reg = ROFFS(iproc_regs, 0x6000 + (addr & 0xfff));
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} else {
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/* Update base address for sub-window 7 */
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subwin_base |= 1; /* Valid bit */
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reg = ROFFS(iproc_regs, BAR0_PAXB_IMAP0_7);
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iproc32_write(shbde, reg, subwin_base);
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/* Read it to make sure the write actually goes through */
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subwin_base = iproc32_read(shbde, reg);
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/* Read register through sub-window 7 */
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reg = ROFFS(iproc_regs, 0x7000 + (addr & 0xfff));
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}
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return iproc32_read(shbde, reg);
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}
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/*
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* Function:
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* shbde_iproc_pci_write
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* Purpose:
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* Write iProc register through PCI BAR 0
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* iproc_regs - memory mapped iProc registers in PCI BAR
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* addr - iProc register address in AXI memory space
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* data - data to write to iProc register
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* Returns:
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* Register value
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*/
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void
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shbde_iproc_pci_write(shbde_hal_t *shbde, void *iproc_regs,
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unsigned int addr, unsigned int data)
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{
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unsigned int subwin_base;
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void *reg;
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shbde_iproc_config_t *icfg = &shbde->icfg;
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if (!iproc_regs) {
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return;
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}
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||
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|
/* Sub-window size is 0x1000 (4K) */
|
||
|
|
subwin_base = (addr & ~0xfff);
|
||
|
|
|
||
|
|
if((icfg->cmic_ver >= 4) && (subwin_base == 0x18013000)) {
|
||
|
|
/* Route the INTC block access through IMAP0_6 */
|
||
|
|
reg = ROFFS(iproc_regs, 0x6000 + (addr & 0xfff));
|
||
|
|
} else {
|
||
|
|
/* Update base address for sub-window 7 */
|
||
|
|
subwin_base |= 1; /* Valid bit */
|
||
|
|
reg = ROFFS(iproc_regs, BAR0_PAXB_IMAP0_7);
|
||
|
|
iproc32_write(shbde, reg, subwin_base);
|
||
|
|
/* Read it to make sure the write actually goes through */
|
||
|
|
subwin_base = iproc32_read(shbde, reg);
|
||
|
|
|
||
|
|
/* Read register through sub-window 7 */
|
||
|
|
reg = ROFFS(iproc_regs, 0x7000 + (addr & 0xfff));
|
||
|
|
}
|
||
|
|
|
||
|
|
iproc32_write(shbde, reg, data);
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
shbde_iproc_pcie_preemphasis_set(shbde_hal_t *shbde, void *iproc_regs,
|
||
|
|
shbde_iproc_config_t *icfg, void *pci_dev)
|
||
|
|
{
|
||
|
|
shbde_mdio_ctrl_t mdio_ctrl, *smc = &mdio_ctrl;
|
||
|
|
unsigned int phy_addr, data;
|
||
|
|
void *reg;
|
||
|
|
unsigned int pcie_cap_base;
|
||
|
|
unsigned short link_stat, link_stat2;
|
||
|
|
|
||
|
|
if (!icfg) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* PHY address for PCIe link */
|
||
|
|
phy_addr = icfg->pcie_phy_addr;
|
||
|
|
if (phy_addr == 0 || icfg->mdio_base_addr == 0) {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Initialize MDIO control */
|
||
|
|
smc->shbde = shbde;
|
||
|
|
smc->regs = iproc_regs;
|
||
|
|
smc->base_addr = icfg->mdio_base_addr;
|
||
|
|
smc->io32_read = shbde_iproc_pci_read;
|
||
|
|
smc->io32_write = shbde_iproc_pci_write;
|
||
|
|
shbde_iproc_mdio_init(smc);
|
||
|
|
|
||
|
|
/* PCIe SerDes Gen1/Gen2 CDR Track Bandwidth Adjustment
|
||
|
|
* for Better Jitter Tolerance
|
||
|
|
*/
|
||
|
|
shbde_iproc_mdio_write(smc, phy_addr, 0x1f, 0x8630);
|
||
|
|
shbde_iproc_mdio_write(smc, phy_addr, 0x13, 0x190);
|
||
|
|
shbde_iproc_mdio_write(smc, phy_addr, 0x19, 0x191);
|
||
|
|
|
||
|
|
if (!icfg->adjust_pcie_preemphasis) {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check to see if the PCIe SerDes deemphasis needs to be changed
|
||
|
|
* based on the advertisement from the root complex
|
||
|
|
*/
|
||
|
|
/* Find PCIe capability base */
|
||
|
|
if (!shbde || !shbde->pcic16_read || !pci_dev) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
pcie_cap_base = shbde_pci_pcie_cap(shbde, pci_dev);
|
||
|
|
if (pcie_cap_base) {
|
||
|
|
link_stat = shbde->pcic16_read(pci_dev,
|
||
|
|
pcie_cap_base + PCI_EXP_LNKSTA);
|
||
|
|
link_stat2 = shbde->pcic16_read(pci_dev,
|
||
|
|
pcie_cap_base + PCI_EXP_LNKSTA2);
|
||
|
|
if (((link_stat & 0xf) == PCI_EXP_LNKSTA_CLS_5_0GB) &&
|
||
|
|
(link_stat2 & PCI_EXP_LNKSTA2_CDL_3_5DB)) {
|
||
|
|
/* Device is operating at Gen2 speeds and RC requested -3.5dB */
|
||
|
|
/* Change the transmitter setting */
|
||
|
|
shbde_iproc_mdio_write(smc, phy_addr, 0x1f, 0x8610);
|
||
|
|
shbde_iproc_mdio_read(smc, phy_addr, 0x17, &data);
|
||
|
|
data &= ~0xf00;
|
||
|
|
data |= 0x700;
|
||
|
|
shbde_iproc_mdio_write(smc, phy_addr, 0x17, data);
|
||
|
|
|
||
|
|
/* Force the PCIe link to retrain */
|
||
|
|
data = 0;
|
||
|
|
REG_FIELD_SET(PAXB_CONFIG_IND_ADDRr, PROTOCOL_LAYERf, data, 0x2);
|
||
|
|
REG_FIELD_SET(PAXB_CONFIG_IND_ADDRr, ADDRESSf, data, 0x4);
|
||
|
|
reg = ROFFS(iproc_regs, BAR0_PAXB_CONFIG_IND_ADDR);
|
||
|
|
iproc32_write(shbde, reg, data);
|
||
|
|
|
||
|
|
reg = ROFFS(iproc_regs, BAR0_PAXB_CONFIG_IND_DATA);
|
||
|
|
data = iproc32_read(shbde, reg);
|
||
|
|
data &= ~0x4000;
|
||
|
|
iproc32_write(shbde, reg, data);
|
||
|
|
data |= 0x4000;
|
||
|
|
iproc32_write(shbde, reg, data);
|
||
|
|
data &= ~0x4000;
|
||
|
|
iproc32_write(shbde, reg, data);
|
||
|
|
|
||
|
|
/* Wait a short while for the retraining to complete */
|
||
|
|
wait_usec(shbde, 1000);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|