405 lines
26 KiB
Plaintext
405 lines
26 KiB
Plaintext
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init start stage low-level
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init set port-map port=0 eth-macro=2 lane=0 max-speed=25g active=true
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init set port-map port=1 eth-macro=2 lane=1 max-speed=25g active=true
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init set port-map port=2 eth-macro=2 lane=2 max-speed=25g active=true
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init set port-map port=3 eth-macro=2 lane=3 max-speed=25g active=true
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init set port-map port=4 eth-macro=3 lane=0 max-speed=25g active=true
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init set port-map port=5 eth-macro=3 lane=1 max-speed=25g active=true
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init set port-map port=6 eth-macro=3 lane=2 max-speed=25g active=true
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init set port-map port=7 eth-macro=3 lane=3 max-speed=25g active=true
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init set port-map port=8 eth-macro=4 lane=0 max-speed=25g active=true
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init set port-map port=9 eth-macro=4 lane=1 max-speed=25g active=true
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init set port-map port=10 eth-macro=4 lane=2 max-speed=25g active=true
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init set port-map port=11 eth-macro=4 lane=3 max-speed=25g active=true
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init set port-map port=12 eth-macro=5 lane=0 max-speed=25g active=true
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init set port-map port=13 eth-macro=5 lane=1 max-speed=25g active=true
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init set port-map port=14 eth-macro=5 lane=2 max-speed=25g active=true
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init set port-map port=15 eth-macro=5 lane=3 max-speed=25g active=true
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init set port-map port=16 eth-macro=8 lane=0 max-speed=25g active=true
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init set port-map port=17 eth-macro=8 lane=1 max-speed=25g active=true
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init set port-map port=18 eth-macro=8 lane=2 max-speed=25g active=true
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init set port-map port=19 eth-macro=8 lane=3 max-speed=25g active=true
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init set port-map port=20 eth-macro=10 lane=0 max-speed=25g active=true
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init set port-map port=21 eth-macro=10 lane=1 max-speed=25g active=true
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init set port-map port=22 eth-macro=10 lane=2 max-speed=25g active=true
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init set port-map port=23 eth-macro=10 lane=3 max-speed=25g active=true
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init set port-map port=24 eth-macro=12 lane=0 max-speed=25g active=true
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init set port-map port=25 eth-macro=12 lane=1 max-speed=25g active=true
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init set port-map port=26 eth-macro=12 lane=2 max-speed=25g active=true
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init set port-map port=27 eth-macro=12 lane=3 max-speed=25g active=true
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init set port-map port=28 eth-macro=14 lane=0 max-speed=25g active=true
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init set port-map port=29 eth-macro=14 lane=1 max-speed=25g active=true
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init set port-map port=30 eth-macro=14 lane=2 max-speed=25g active=true
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init set port-map port=31 eth-macro=14 lane=3 max-speed=25g active=true
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init set port-map port=32 eth-macro=16 lane=0 max-speed=25g active=true
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init set port-map port=33 eth-macro=16 lane=1 max-speed=25g active=true
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init set port-map port=34 eth-macro=16 lane=2 max-speed=25g active=true
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init set port-map port=35 eth-macro=16 lane=3 max-speed=25g active=true
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init set port-map port=36 eth-macro=17 lane=0 max-speed=25g active=true
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init set port-map port=37 eth-macro=17 lane=1 max-speed=25g active=true
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init set port-map port=38 eth-macro=17 lane=2 max-speed=25g active=true
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init set port-map port=39 eth-macro=17 lane=3 max-speed=25g active=true
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init set port-map port=40 eth-macro=18 lane=0 max-speed=25g active=true
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init set port-map port=41 eth-macro=18 lane=1 max-speed=25g active=true
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init set port-map port=42 eth-macro=18 lane=2 max-speed=25g active=true
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init set port-map port=43 eth-macro=18 lane=3 max-speed=25g active=true
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init set port-map port=44 eth-macro=19 lane=0 max-speed=25g active=true
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init set port-map port=45 eth-macro=19 lane=1 max-speed=25g active=true
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init set port-map port=46 eth-macro=19 lane=2 max-speed=25g active=true
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init set port-map port=47 eth-macro=19 lane=3 max-speed=25g active=true
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init set port-map port=48 eth-macro=20 lane=0 max-speed=100g active=true
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init set port-map port=49 eth-macro=21 lane=0 max-speed=100g active=true
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init set port-map port=50 eth-macro=26 lane=0 max-speed=100g active=true
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init set port-map port=51 eth-macro=27 lane=0 max-speed=100g active=true
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init set port-map port=52 eth-macro=28 lane=0 max-speed=100g active=true
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init set port-map port=53 eth-macro=29 lane=0 max-speed=100g active=true
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init set port-map port=129 eth-macro=0 lane=1 max-speed=10g active=true guarantee=true cpi=true
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init set port-map port=130 eth-macro=0 lane=0 max-speed=10g active=true guarantee=true cpi=true init-done=true
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init start stage task-rsrc
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init start stage module
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init start stage task
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phy set lane-swap portlist=0 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=1 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=2 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=3 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=4 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=5 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=6 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=7 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=8 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=9 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=10 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=11 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=12 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=13 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=14 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=15 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=16 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=17 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=18 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=19 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=20 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=21 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=22 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=23 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=24 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=25 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=26 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=27 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=28 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=29 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=30 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=31 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=32 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=33 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=34 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=35 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=36 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=37 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=38 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=39 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=40 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=41 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=42 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=43 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=44 lane-cnt=1 property=tx data=0x0
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phy set lane-swap portlist=45 lane-cnt=1 property=tx data=0x1
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phy set lane-swap portlist=46 lane-cnt=1 property=tx data=0x2
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phy set lane-swap portlist=47 lane-cnt=1 property=tx data=0x3
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phy set lane-swap portlist=48-53 lane-cnt=4 property=tx data=0x03.02.01.00
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phy set lane-swap portlist=0 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=1 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=2 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=3 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=4 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=5 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=6 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=7 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=8 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=9 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=10 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=11 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=12 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=13 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=14 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=15 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=16 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=17 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=18 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=19 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=20 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=21 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=22 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=23 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=24 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=25 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=26 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=27 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=28 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=29 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=30 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=31 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=32 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=33 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=34 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=35 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=36 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=37 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=38 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=39 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=40 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=41 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=42 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=43 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=44 lane-cnt=1 property=rx data=0x1
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phy set lane-swap portlist=45 lane-cnt=1 property=rx data=0x2
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phy set lane-swap portlist=46 lane-cnt=1 property=rx data=0x3
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phy set lane-swap portlist=47 lane-cnt=1 property=rx data=0x0
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phy set lane-swap portlist=48-53 lane-cnt=4 property=rx data=0x03.02.01.00
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phy set polarity-rev portlist=0 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=1 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=2 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=3 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=4 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=5 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=6 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=7 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=8 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=9 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=10 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=11 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=12 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=13 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=14 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=15 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=16 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=17 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=18 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=19 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=20 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=21 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=22 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=23 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=24 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=25 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=26 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=27 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=28 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=29 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=30 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=31 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=32 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=33 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=34 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=35 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=36 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=37 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=38 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=39 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=40 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=41 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=42 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=43 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=44 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=45 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=46 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=47 lane-cnt=1 property=tx data=0x0
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phy set polarity-rev portlist=48 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=49 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=50 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=51 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=52 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=53 lane-cnt=4 property=tx data=0x0.0.0.0
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phy set polarity-rev portlist=0 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=1 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=2 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=3 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=4 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=5 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=6 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=7 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=8 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=9 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=10 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=11 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=12 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=13 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=14 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=15 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=16 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=17 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=18 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=19 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=20 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=21 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=22 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=23 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=24 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=25 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=26 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=27 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=28 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=29 lane-cnt=1 property=rx data=0x0
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phy set polarity-rev portlist=30 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=31 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=32 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=33 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=34 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=35 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=36 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=37 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=38 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=39 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=40 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=41 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=42 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=43 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=44 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=45 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=46 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=47 lane-cnt=1 property=rx data=0x0
|
||
|
phy set polarity-rev portlist=48 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set polarity-rev portlist=49 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set polarity-rev portlist=50 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set polarity-rev portlist=51 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set polarity-rev portlist=52 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set polarity-rev portlist=53 lane-cnt=4 property=rx data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=0 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=4 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=8 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=12 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=16 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=20 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=24 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=28 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=32 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=36 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=40 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=44 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=48 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=49 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=50 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=51 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=52 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c2 data=0x0.0.0.0
|
||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=cn1 data=0x4.4.4.4
|
||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c0 data=0x1E.1E.1E.1E
|
||
|
phy set pre-emphasis portlist=53 lane-cnt=4 property=c1 data=0x2.2.2.2
|
||
|
phy set mdio portlist=0 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=1 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=2 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=3 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=4 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=5 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=6 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=7 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=8 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=9 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=10 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=11 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=12 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=13 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=14 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=15 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=16 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=17 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=18 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=19 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=20 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=21 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=22 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=23 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=24 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=25 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=26 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=27 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=28 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=29 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=30 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=31 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=32 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=33 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=34 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=35 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=36 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=37 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=38 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=39 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=40 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=41 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=42 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=43 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=44 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=45 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=46 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=47 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=48 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=49 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=50 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=51 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=52 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=53 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=129 devad=0x1E addr=0x2 data=0x0000
|
||
|
phy set mdio portlist=130 devad=0x1E addr=0x2 data=0x0000
|
||
|
port set property portlist=0-47 speed=25g
|
||
|
port set property portlist=48-53 speed=100g
|
||
|
port set property portlist=129-130 speed=10g
|
||
|
port set property portlist=0-47 medium-type=cr
|
||
|
port set property portlist=48-53 medium-type=cr4
|
||
|
port set property portlist=129-130 medium-type=kr
|
||
|
port set adver portlist=129-130 speed-10g-kr
|
||
|
port set property portlist=129-130 an=enable
|
||
|
port set property portlist=129-130 admin=enable
|
||
|
port set property portlist=0-53 admin=disable
|