394 lines
11 KiB
C
394 lines
11 KiB
C
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/*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to
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* you under the terms of the GNU General Public License version 2 (the
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* "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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* with the following added to such license:
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*
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* As a special exception, the copyright holders of this software give
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* you permission to link this software with independent modules, and to
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* copy and distribute the resulting executable under terms of your
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* choice, provided that you also meet, for each linked independent
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* module, the terms and conditions of the license of that module. An
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* independent module is a module which is not derived from this
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* software. The special exception does not apply to any modifications
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* of the software.
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*/
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/*
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* $Id: $
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* $Copyright: (c) 2014 Broadcom Corp.
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* All Rights Reserved.$
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*
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*/
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#include <shbde_pci.h>
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/* PCIe capabilities */
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#ifndef PCI_CAPABILITY_LIST
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#define PCI_CAPABILITY_LIST 0x34
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#endif
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#ifndef PCI_CAP_ID_EXP
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#define PCI_CAP_ID_EXP 0x10
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#endif
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#ifndef PCI_EXP_DEVCAP
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#define PCI_EXP_DEVCAP 4
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#endif
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#ifndef PCI_EXP_DEVCTL
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#define PCI_EXP_DEVCTL 8
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#endif
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#ifndef PCI_EXT_CAP_START
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#define PCI_EXT_CAP_START 0x100
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#endif
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#ifndef PCI_EXT_CAP_ID
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#define PCI_EXT_CAP_ID(_hdr) (_hdr & 0x0000ffff)
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#endif
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#ifndef PCI_EXT_CAP_VER
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#define PCI_EXT_CAP_VER(_hdr) ((_hdr >> 16) & 0xf)
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#endif
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#ifndef PCI_EXT_CAP_NEXT
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#define PCI_EXT_CAP_NEXT(_hdr) ((_hdr >> 20) & 0xffc)
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#endif
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#ifndef PCI_EXT_CAP_ID_VNDR
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#define PCI_EXT_CAP_ID_VNDR 0x0b
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#endif
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#define LOG_OUT(_shbde, _lvl, _str, _prm) \
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if ((_shbde)->log_func) { \
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(_shbde)->log_func(_lvl, _str, _prm); \
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}
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#define LOG_ERR(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_ERR, _str, _prm)
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#define LOG_WARN(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_WARN, _str, _prm)
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#define LOG_DBG(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_DBG, _str, _prm)
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#ifndef NULL
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#define NULL (void *)0
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#endif
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/*
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* Warpper functions with null-pointer checks.
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*/
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static unsigned int
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pcic16_read(shbde_hal_t *shbde, void *pci_dev,
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unsigned int addr)
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{
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if (!shbde || !shbde->pcic16_read) {
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return 0;
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}
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return shbde->pcic16_read(pci_dev, addr);
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}
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static void
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pcic16_write(shbde_hal_t *shbde, void *pci_dev,
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unsigned int addr, unsigned int data)
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{
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if (!shbde || !shbde->pcic16_write) {
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return;
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}
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shbde->pcic16_write(pci_dev, addr, data);
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}
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static unsigned int
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pcic32_read(shbde_hal_t *shbde, void *pci_dev,
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unsigned int addr)
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{
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if (!shbde || !shbde->pcic32_read) {
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return 0;
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}
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return shbde->pcic32_read(pci_dev, addr);
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}
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static void *
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pci_parent_device_get(shbde_hal_t *shbde, void *pci_dev)
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{
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if (!shbde || !shbde->pci_parent_device_get) {
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return NULL;
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}
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return shbde->pci_parent_device_get(pci_dev);
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}
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/*
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* Function:
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* shbde_pci_pcie_cap
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* Purpose:
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* Return offset of PCIe capabilities in PCI configuration space
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* dev - PCI device handle (passed back to PCI HAL functions)
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* Returns:
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* PCI_CAP_ID_EXP offset in PCI configuration space if PCIe, otherwise 0
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*/
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unsigned int
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shbde_pci_pcie_cap(shbde_hal_t *shbde, void *pci_dev)
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{
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unsigned int cap_base, rval;
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cap_base = pcic16_read(shbde, pci_dev, PCI_CAPABILITY_LIST);
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while (cap_base) {
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rval = pcic16_read(shbde, pci_dev, cap_base);
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if ((rval & 0xff) == PCI_CAP_ID_EXP) {
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break;
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}
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cap_base = (rval >> 8) & 0xff;
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}
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return cap_base;
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}
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/*
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* Function:
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* shbde_pci_is_pcie
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* Purpose:
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* Check if PCI device is PCIe device
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* dev - PCI device handle (passed back to PCI HAL functions)
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* Returns:
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* 1 if PCIe, otherwise 0
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*/
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int
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shbde_pci_is_pcie(shbde_hal_t *shbde, void *pci_dev)
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{
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return shbde_pci_pcie_cap(shbde, pci_dev) ? 1 : 0;
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}
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/*
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* Function:
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* shbde_pci_is_iproc
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* Purpose:
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* Check if PCI device is iProc-based
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* dev - PCI device handle (passed back to PCI HAL functions)
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* cmic_bar - (OUT) PCI BAR which contains switch CMIC registers
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* Returns:
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* 1 if iProc-based, otherwise 0
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*/
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int
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shbde_pci_is_iproc(shbde_hal_t *shbde, void *pci_dev, int *cmic_bar)
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{
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unsigned int cap_base, rval;
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if (!shbde_pci_is_pcie(shbde, pci_dev)) {
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return 0;
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}
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/* Look for PCIe vendor-specific extended capability (VSEC) */
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cap_base = PCI_EXT_CAP_START;
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while (cap_base) {
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rval = pcic32_read(shbde, pci_dev, cap_base);
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if (rval == 0xffffffff) {
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/* Assume PCI HW read error */
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return 0;
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}
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if (PCI_EXT_CAP_ID(rval) == PCI_EXT_CAP_ID_VNDR) {
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break;
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}
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cap_base = PCI_EXT_CAP_NEXT(rval);
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}
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if (cap_base) {
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/*
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* VSEC layout:
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*
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* 0x00: PCI Express Extended Capability Header
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* 0x04: Vendor-Specific Header
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* 0x08: Vendor-Specific Register 1
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* 0x0c: Vendor-Specific Register 2
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* ...
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* 0x24: Vendor-Specific Register 8
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*/
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/* 32'b // 31:12=0 Reserved; 11:08=CMIC BAR; 07:00=iProc Configuration ID */
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rval = pcic32_read(shbde, pci_dev, cap_base + 8);
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LOG_DBG(shbde, "Found VSEC", rval);
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/* Determine PCI BAR of CMIC */
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*cmic_bar = 0;
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if ((rval & 0x100) == 0x100) {
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*cmic_bar = 2;
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}
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/* Assume iProc device */
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return 1;
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}
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return 0;
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}
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/*
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* Function:
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* shbde_pci_iproc_version_get
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* Purpose:
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* Get iproc, cmic versions and revisions
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* dev - PCI device handle (passed back to PCI HAL functions)
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* iproc_ver - (OUT) iProc version
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* cmic_ver - (OUT) CMIC version
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* cmic_rev - (OUT) CMIC revision
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* Returns:
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* 1 for no error, otherwise 0
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*/
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int
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shbde_pci_iproc_version_get(shbde_hal_t *shbde, void *pci_dev,
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unsigned int *iproc_ver,
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unsigned int *cmic_ver,
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unsigned int *cmic_rev)
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{
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unsigned int cap_base, rval;
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if (!shbde_pci_is_pcie(shbde, pci_dev)) {
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return 0;
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}
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/* Look for PCIe vendor-specific extended capability (VSEC) */
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cap_base = PCI_EXT_CAP_START;
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while (cap_base) {
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rval = pcic32_read(shbde, pci_dev, cap_base);
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if (rval == 0xffffffff) {
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/* Assume PCI HW read error */
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return 0;
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}
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if (PCI_EXT_CAP_ID(rval) == PCI_EXT_CAP_ID_VNDR) {
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break;
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}
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cap_base = PCI_EXT_CAP_NEXT(rval);
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}
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if (cap_base) {
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/*
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* VSEC layout:
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*
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* 0x00: PCI Express Extended Capability Header
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* 0x04: Vendor-Specific Header
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* 0x08: Vendor-Specific Register 1
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* 0x0c: Vendor-Specific Register 2
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* ...
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* 0x24: Vendor-Specific Register 8
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*/
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/* Read PCIe Vendor Specific Register 1 */
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/* VENODR REG FORMAT
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* [7:0] iProc Rev = 8'h0E (for P14)
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* [11:8] CMIC BAR = 4'h1 (BAR64-1)
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* [15:12] CMIC Version = 4'h4
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* [19:16] CMIC Rev = 4'h1
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* [22:20] SBUS Version = 4'h4
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*/
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rval = pcic32_read(shbde, pci_dev, cap_base + 8);
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LOG_DBG(shbde, "Found VSEC", rval);
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/* Determine PCI BAR of CMIC */
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*iproc_ver = rval & 0xff;
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*cmic_ver = (rval >> 12) & 0xf;
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*cmic_rev = (rval >> 16) & 0xf;
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return 1;
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}
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return 0;
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}
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/*
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* Function:
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* shbde_pci_max_payload_set
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* Purpose:
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* Set PCIe maximum payload
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* Parameters:
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* shbde - pointer to initialized hardware abstraction module
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* dev - PCI device handle (passed back to PCI HAL functions)
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* maxpayload - maximum payload (in byte)
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* Returns:
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* -1 if error, otherwise 0
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* Notes:
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* If not PCIe device, set the PCI retry count to infinte instead.
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*/
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int
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shbde_pci_max_payload_set(shbde_hal_t *shbde, void *pci_dev, int maxpayload)
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{
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unsigned int cap_base, parent_cap_base;
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unsigned int devcap, devctl, parent_devctl;
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int max_val, max_cap, parent_max_val;
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void *parent_pci_dev;
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cap_base = shbde_pci_pcie_cap(shbde, pci_dev);
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if (cap_base == 0) {
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/* Not PCIe */
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return 0;
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}
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/* Get current device control settings */
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devctl = pcic16_read(shbde, pci_dev, cap_base + PCI_EXP_DEVCTL);
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/* Get current max payload setting */
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max_val = (devctl >> 5) & 0x7;
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if (maxpayload) {
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/* Get encoding from byte value */
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max_val = 0;
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while ((1 << (max_val + 7)) < maxpayload) {
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max_val++;
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}
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LOG_DBG(shbde, "Set max payload size", maxpayload);
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LOG_DBG(shbde, "Set max payload val", max_val);
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/* Get max supported payload size */
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devcap = pcic16_read(shbde, pci_dev, cap_base + PCI_EXP_DEVCAP);
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max_cap = (devcap & 0x7);
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/* Do not exceed device capabilities */
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if (max_val > max_cap) {
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max_val = max_cap;
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LOG_DBG(shbde,
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"Payload size exceeds device capability",
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maxpayload);
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}
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/* Get currently set max payload size for the parent device
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* in the PCI tree (if it exists).
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*/
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parent_pci_dev = pci_parent_device_get(shbde, pci_dev);
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if (parent_pci_dev != NULL) {
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parent_cap_base = shbde_pci_pcie_cap(shbde, parent_pci_dev);
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parent_devctl = pcic16_read(shbde,
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parent_pci_dev,
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parent_cap_base + PCI_EXP_DEVCTL);
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parent_max_val = (parent_devctl >> 5) & 0x7;
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/* Do not exceed current parent max payload setting (our device
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* should have an MPS setting <= current parent MPS setting in
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* the tree of PCIe devices).
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*/
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if (max_val > parent_max_val) {
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max_val = parent_max_val;
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LOG_DBG(shbde,
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"Payload size exceeds current parent device setting",
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maxpayload);
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}
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}
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/* Update max payload size */
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devctl &= ~(0x7 << 5);
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devctl |= (max_val) << 5;
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||
|
|
/* Update max request size */
|
||
|
|
devctl &= ~(0x7 << 12);
|
||
|
|
devctl |= (max_val << 12);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Always disable relaxed ordering */
|
||
|
|
devctl &= ~(1 << 4);
|
||
|
|
|
||
|
|
/* Update device control settings */
|
||
|
|
pcic16_write(shbde, pci_dev, cap_base + PCI_EXP_DEVCTL, devctl);
|
||
|
|
|
||
|
|
/* Warn if non-default setting is used */
|
||
|
|
if (max_val > 0) {
|
||
|
|
LOG_WARN(shbde,
|
||
|
|
"Selected payload size may not be supported by all "
|
||
|
|
"PCIe bridges by default.",
|
||
|
|
(1 << (max_val + 7)));
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|