sonic-buildimage/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini

#  PG lossless profiles.
# speed cable  size   xon    xoff   threshold
  10000    5m 45056  19456  25600          0
  25000    5m 48128  19456  28672          0
  40000    5m 50176  19456  30720          0
  50000    5m 52224  19456  32768          0
 100000    5m 60416  19456  40960          0
  10000   40m 46080  19456  26624          0
  25000   40m 50176  19456  30720          0
  40000   40m 53248  19456  33792          0
  50000   40m 56320  19456  36864          0
 100000   40m 67584  19456  48128          0
  10000  300m 51200  19456  31744          0
  25000  300m 63488  19456  44032          0
  40000  300m 74752  19456  55296          0
  50000  300m 82944  19456  63488          0
 100000  300m 121856 19456  102400         0
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194) This is to backport the #4886 to 201911 Calculate pool size in t1 as 24 * downlink port + 8 * uplink port - Take both port and peer MTU into account when calculating headroom - Worst case factor is decreased to 50% - Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports - Mellanox-SN2700 (C32) - t0: 16 * 100G/5m + 16 * 100G/40m - t1: 16 * 100G/40m + 16 * 100G/300m Signed-off-by: Stephen Sun <stephens@nvidia.com> 2020-08-15 09:52:28 -05:00			`# PG lossless profiles.`
			`# speed cable size xon xoff threshold`
			`10000 5m 45056 19456 25600 0`
			`25000 5m 48128 19456 28672 0`
			`40000 5m 50176 19456 30720 0`
			`50000 5m 52224 19456 32768 0`
			`100000 5m 60416 19456 40960 0`
			`10000 40m 46080 19456 26624 0`
			`25000 40m 50176 19456 30720 0`
			`40000 40m 53248 19456 33792 0`
			`50000 40m 56320 19456 36864 0`
			`100000 40m 67584 19456 48128 0`
			`10000 300m 51200 19456 31744 0`
			`25000 300m 63488 19456 44032 0`
			`40000 300m 74752 19456 55296 0`
			`50000 300m 82944 19456 63488 0`
			`100000 300m 121856 19456 102400 0`