591 lines
16 KiB
C
591 lines
16 KiB
C
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#include "i2c-mei_rw.h"
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#define MicroSecondDelay(time) udelay(time)
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/****** Parameter *****/
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/****** Struct *****/
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typedef struct
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{
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volatile UINT32 CB_WW; // Circular Buffer Write Window
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volatile UINT32 H_CSR; // Host Control and Status Register
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volatile UINT32 CB_RW; // Circular Buffer Read Window
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volatile UINT32 ME_CSR; // ME Control and Status Register (read only)
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} HECI_MBAR_REGS;
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typedef union
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{
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UINT32 DWord;
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struct
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{
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UINT32 H_IE : 1, // 0 - Interrupt Enable ME
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H_IS : 1, // 1 - Interrupt Status ME
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H_IG : 1, // 2 - Interrupt Generate
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H_RDY : 1, // 3 - Ready
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H_RST : 1, // 4 - Reset
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Reserved: 3, // 5~7
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H_CBRP : 8, // 8~15 - CB Read Pointer
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H_CBWP : 8, // 16~23 - CB Write Pointer
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H_CBD : 8; // 24~31 - Circular Buffer Depth
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} Bits;
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} HECI_HOST_CSR;
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// HECI_MBAR_REGS::ME_CSR - ME Control and Status Register
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typedef union
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{
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UINT32 DWord;
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struct
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{
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UINT32 ME_IE : 1, // 0 - Interrupt Enable (Host Read Access)
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ME_IS : 1, // 1 - Interrupt Status (Host Read Access)
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ME_IG : 1, // 2 - Interrupt Generate (Host Read Access)
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ME_RDY : 1, // 3 - Ready (Host Read Access)
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ME_RST : 1, // 4 - Reset (Host Read Access)
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Reserved: 3, // 5~7
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ME_CBRP : 8, // 8~15 - CB Read Pointer (Host Read Access)
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ME_CBWP : 8, // 16~23 - CB Write Pointer (Host Read Access)
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ME_CBD : 8; // 24~31 - Circular Buffer Depth (Host Read Access)
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} Bits;
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} HECI_ME_CSR;
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/****** Function *****/
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VOID* HeciMbarRead(IN HECI_DEVICE *pThis);
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VOID HeciTrace(IN HECI_DEVICE*, IN CHAR8*, IN HECI_MSG_HEADER*, IN INT32);
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EFI_STATUS HeciInit ( HECI_DEVICE *pThis,
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UINT32 *pTimeout)
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{
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EFI_STATUS Status = EFI_SUCCESS;
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UINT32 Timeout = 0;
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HECI_HOST_CSR sHCsr;
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HECI_ME_CSR sMeCsr;
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HECI_MBAR_REGS *pMbarRegs;
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VOID *pAddrPoint;
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if (pThis == NULL || (pThis->Mbar & 0xF) != 0 || pThis->Hidm > HECI_HIDM_LAST)
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{
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printk("Heci Init Failed");
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return EFI_INVALID_PARAMETER;
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}
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if (pTimeout != NULL)
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{
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Timeout = *pTimeout;
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}
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// HECI vendor and device information away
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pThis->PciCfg = PCI_LIB_ADDRESS(pThis->Bus, pThis->Dev, pThis->Fun, 0);
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pThis->Vid = PciRead16(pThis->PciCfg + HECI_REG_VENDORID);
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pThis->Did = PciRead16(pThis->PciCfg + HECI_REG_DEVICEID);
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if (pThis->Vid != 0x8086)
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{
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printk("[HECI] Init failed, PCI device %d/%d/%d not valid HECI (%2X-%2X)\n",
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pThis->Bus, pThis->Dev, pThis->Fun, pThis->Vid, pThis->Did);
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return EFI_DEVICE_ERROR;
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}
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// Check MBAR,
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pAddrPoint = HeciMbarRead(pThis);
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pMbarRegs = (HECI_MBAR_REGS*)ioremap_nocache(pAddrPoint, 0x1000);
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if (pMbarRegs == NULL)
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{
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printk("[HECI-%d] Init failed (device disabled)\n", pThis->Fun);
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printk("Check MBAR Failed");
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Status = EFI_DEVICE_ERROR;
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goto GO_FAIL;
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}
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// Set HECI interrupt delivery mode.
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sHCsr.DWord = pMbarRegs->H_CSR;
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sHCsr.Bits.H_IE = 0;
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pMbarRegs->H_CSR = sHCsr.DWord;
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PciWrite8(pThis->PciCfg + HECI_REG_HIDM, pThis->Hidm);
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// Check HECI was free
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sMeCsr.DWord = pMbarRegs->ME_CSR;
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if (!sMeCsr.Bits.ME_RDY)
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{
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Status = HecClearQue(pThis, &Timeout);
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}
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else
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{
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if (!sHCsr.Bits.H_RDY)
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{
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sHCsr.Bits.H_IG = 1;
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sHCsr.Bits.H_RDY = 1;
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sHCsr.Bits.H_RST = 0;
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pMbarRegs->H_CSR = sHCsr.DWord;
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}
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pThis->HMtu = sHCsr.Bits.H_CBD * sizeof(UINT32) - sizeof(HECI_MSG_HEADER);
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pThis->MeMtu = sMeCsr.Bits.ME_CBD * sizeof(UINT32) - sizeof(HECI_MSG_HEADER);
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}
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GO_FAIL:
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if (pTimeout != NULL)
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{
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*pTimeout = Timeout;
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}
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pThis->Mefs1.DWord = HeciPciReadMefs1();
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iounmap((VOID *)pMbarRegs);
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return Status;
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}
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EFI_STATUS HecClearQue ( HECI_DEVICE *pThis,
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UINT32 *pTimeout)
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{
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EFI_STATUS Status;
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UINT32 Timeout = 0;
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HECI_HOST_CSR sHCsr;
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HECI_ME_CSR sMeCsr;
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HECI_MBAR_REGS *pMbarRegs;
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VOID *pAddrPoint;
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if (pThis == NULL)
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{
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printk("Failed");
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return EFI_INVALID_PARAMETER;
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}
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// Check for HECI availability on PCI
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pAddrPoint = HeciMbarRead(pThis);
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pMbarRegs = (HECI_MBAR_REGS*)ioremap_nocache(pAddrPoint, 0x1000);
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printk("pMbarRegs: %x\n", pMbarRegs);
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if (pMbarRegs == NULL)
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{
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printk("[HECI-%d] Reset failed (device disabled)\n", pThis->Fun);
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printk("Failed");
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return EFI_DEVICE_ERROR;
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}
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if (pTimeout != NULL)
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{
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Timeout = *pTimeout;
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}
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printk("[HECI-%d] Resetting HECI interface (CSR %X/%X)\n",
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pThis->Fun, pMbarRegs->H_CSR, pMbarRegs->ME_CSR);
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sHCsr.DWord = pMbarRegs->H_CSR;
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if (!sHCsr.Bits.H_RST)
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{
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sHCsr.Bits.H_RST = 1;
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sHCsr.Bits.H_IG = 1;
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pMbarRegs->H_CSR = sHCsr.DWord;
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}
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// Wait for H_RDY cleared to make sure that the reset started.
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while (1)
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{
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sHCsr.DWord = pMbarRegs->H_CSR;
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if (!sHCsr.Bits.H_RDY)
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{
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break;
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}
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if (Timeout == 0)
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{
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printk("[HECI-%d] Reset failed (timeout)(CSR %X/%X)\n",
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pThis->Fun, pMbarRegs->H_CSR, pMbarRegs->ME_CSR);
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Status = EFI_TIMEOUT;
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goto GO_FAIL;
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}
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MicroSecondDelay(HECI_TIMEOUT_UNIT);
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Timeout--;
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}
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// Wait for ME to perform reset and signal it is ready.
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while (1)
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{
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sMeCsr.DWord = pMbarRegs->ME_CSR;
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if (sMeCsr.Bits.ME_RDY)
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{
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break;
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}
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if (Timeout == 0)
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{
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printk("[HECI-%d] Reset failed (timeout)(CSR %X/%X)\n",
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pThis->Fun, pMbarRegs->H_CSR, pMbarRegs->ME_CSR);
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Status = EFI_TIMEOUT;
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goto GO_FAIL;
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}
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MicroSecondDelay(HECI_TIMEOUT_UNIT);
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Timeout--;
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}
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// ME side is ready, signal host side is ready too.
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sHCsr.DWord = pMbarRegs->H_CSR;
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sHCsr.Bits.H_RST = 0;
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sHCsr.Bits.H_RDY = 1;
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sHCsr.Bits.H_IG = 1;
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pMbarRegs->H_CSR = sHCsr.DWord;
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// Update MTU, ME could change it during reset.
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pThis->HMtu = sHCsr.Bits.H_CBD * sizeof(UINT32) - sizeof(HECI_MSG_HEADER);
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pThis->MeMtu = sMeCsr.Bits.ME_CBD * sizeof(UINT32) - sizeof(HECI_MSG_HEADER);
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Status = EFI_SUCCESS;
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GO_FAIL:
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if (pTimeout != NULL)
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{
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*pTimeout = Timeout;
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}
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pThis->Mefs1.DWord = HeciPciReadMefs1();
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iounmap((VOID *)pMbarRegs);
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return Status;
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}
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EFI_STATUS HeciMsgRecv ( HECI_DEVICE *pThis,
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UINT32 *pTimeout,
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HECI_MSG_HEADER *pMsgBuf,
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UINT32 *pBufLen )
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{
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EFI_STATUS Status = EFI_SUCCESS;
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UINT32 Timeout = 0;
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UINT32 DWord, dwDataReads, dwBufLen;
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UINT8 bFilledSlots, bMsgLen = 0;
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HECI_HOST_CSR sHCsr;
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HECI_ME_CSR sMeCsr;
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HECI_MBAR_REGS *pMbarRegs;
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VOID *pAddrPoint;
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if (pThis == NULL || pMsgBuf == NULL ||
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pBufLen == NULL || *pBufLen < sizeof(HECI_MSG_HEADER))
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{
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printk("Heci MsgRecv Failed\n");
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return EFI_INVALID_PARAMETER;
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}
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// Check for HECI availability on PCI
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pAddrPoint = HeciMbarRead(pThis);
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pMbarRegs = (HECI_MBAR_REGS*)ioremap_nocache(pAddrPoint, 0x1000);
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if (pMbarRegs == NULL)
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{
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printk("[HECI-%d] Receive failed (device disabled)\n", pThis->Fun);
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printk("pMbarRegs Failed\n");
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return EFI_DEVICE_ERROR;
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}
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if (pTimeout != NULL)
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{
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Timeout = *pTimeout;
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}
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// read from queue.
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dwBufLen = *pBufLen;
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*pBufLen = dwDataReads = 0;
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while (1)
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{
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sHCsr.DWord = pMbarRegs->H_CSR;
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sMeCsr.DWord = pMbarRegs->ME_CSR;
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bFilledSlots = (UINT8)((INT8)sMeCsr.Bits.ME_CBWP - (INT8)sMeCsr.Bits.ME_CBRP);
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// Is it ready ?
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if (!sMeCsr.Bits.ME_RDY || !sHCsr.Bits.H_RDY || bFilledSlots > sHCsr.Bits.H_CBD)
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{
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Status = HecClearQue(pThis, &Timeout);
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if (EFI_ERROR(Status))
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{
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goto GO_FAIL;
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}
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continue;
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}
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// Read queue
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while (bFilledSlots-- > 0)
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{
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DWord = pMbarRegs->CB_RW;
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if (*pBufLen < dwBufLen)
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{
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if (dwDataReads < dwBufLen / sizeof(UINT32))
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{
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((UINT32*)pMsgBuf)[dwDataReads] = DWord;
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*pBufLen += sizeof(UINT32);
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}
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else
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{
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switch (dwBufLen % sizeof(UINT32))
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{
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case 3: ((UINT8*)pMsgBuf)[*pBufLen + 2] = (UINT8)(DWord >> 16);
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case 2: ((UINT8*)pMsgBuf)[*pBufLen + 1] = (UINT8)(DWord >> 8);
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case 1: ((UINT8*)pMsgBuf)[*pBufLen + 0] = (UINT8)DWord;
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}
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*pBufLen += dwBufLen % sizeof(UINT32);
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}
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}
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else
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{
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printk("[HECI-%d] Message 0x%08X exceeds buffer size (%dB)\n",
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pThis->Fun, pMsgBuf[0].DWord, dwBufLen);
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}
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dwDataReads++;
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// Read message length.
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if (bMsgLen == 0)
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{
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bMsgLen = (UINT8)((pMsgBuf[0].Bits.Length + sizeof(UINT32) - 1) / sizeof(UINT32));
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bMsgLen++; // One more double word for message header
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//
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// Sanity check. If message length exceeds queue length this is
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// not valid header. We are out of synch, let's reset the queue.
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//
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if (bMsgLen > sMeCsr.Bits.ME_CBD)
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{
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printk("[HECI-%d] 0x%08X does not seem to be msg header, reseting...\n",
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pThis->Fun, pMsgBuf[0].DWord);
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Status = HecClearQue(pThis, &Timeout);
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if (EFI_ERROR(Status))
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{
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goto GO_FAIL;
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}
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*pBufLen = dwDataReads = bMsgLen = 0;
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break; // while (bFilledSlots)
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}
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}
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// If message is complete set interrupt to ME to let it know that next
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// message can be sent and exit.
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if (dwDataReads >= bMsgLen)
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{
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sMeCsr.DWord = pMbarRegs->ME_CSR;
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sHCsr.DWord = pMbarRegs->H_CSR;
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if (!sMeCsr.Bits.ME_RDY)
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{
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HecClearQue(pThis, &Timeout);
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Status = EFI_ABORTED;
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|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
HeciTrace(pThis, " Got msg: ", pMsgBuf, *pBufLen);
|
||
|
|
sHCsr.Bits.H_IG = 1;
|
||
|
|
pMbarRegs->H_CSR = sHCsr.DWord;
|
||
|
|
}
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (Timeout == 0)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Receive failed (timeout)\n", pThis->Fun);
|
||
|
|
Status = EFI_TIMEOUT;
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
MicroSecondDelay(HECI_TIMEOUT_UNIT);
|
||
|
|
Timeout--;
|
||
|
|
}
|
||
|
|
GO_FAIL:
|
||
|
|
if (pTimeout != NULL)
|
||
|
|
{
|
||
|
|
*pTimeout = Timeout;
|
||
|
|
}
|
||
|
|
pThis->Mefs1.DWord = HeciPciReadMefs1();
|
||
|
|
iounmap((VOID *)pMbarRegs);
|
||
|
|
return Status;
|
||
|
|
}
|
||
|
|
|
||
|
|
EFI_STATUS HeciMsgSend ( HECI_DEVICE *pThis,
|
||
|
|
UINT32 *pTimeout,
|
||
|
|
HECI_MSG_HEADER *pMessage)
|
||
|
|
{
|
||
|
|
EFI_STATUS Status;
|
||
|
|
UINT32 Timeout = 0;
|
||
|
|
UINT8 bEmptySlots;
|
||
|
|
UINT8 i, bMsgLen;
|
||
|
|
HECI_HOST_CSR sHCsr;
|
||
|
|
HECI_ME_CSR sMeCsr;
|
||
|
|
HECI_MBAR_REGS *pMbarRegs;
|
||
|
|
VOID *pAddrPoint;
|
||
|
|
|
||
|
|
if (pThis == NULL || pMessage == NULL)
|
||
|
|
{
|
||
|
|
printk("HeciMsgSend Failed\n");
|
||
|
|
return EFI_INVALID_PARAMETER;
|
||
|
|
}
|
||
|
|
HeciTrace(pThis, "Send msg: ", pMessage, sizeof(HECI_MSG_HEADER) + pMessage->Bits.Length);
|
||
|
|
|
||
|
|
// Check for HECI availability
|
||
|
|
pAddrPoint = HeciMbarRead(pThis);
|
||
|
|
pMbarRegs = (HECI_MBAR_REGS*)ioremap_nocache(pAddrPoint, 0x1000);
|
||
|
|
if (pMbarRegs == NULL)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Send failed (device disabled)\n", pThis->Fun);
|
||
|
|
printk("Failed\n");
|
||
|
|
return EFI_DEVICE_ERROR;
|
||
|
|
}
|
||
|
|
if (pTimeout != NULL)
|
||
|
|
{
|
||
|
|
Timeout = *pTimeout;
|
||
|
|
}
|
||
|
|
|
||
|
|
bMsgLen = (UINT8)((pMessage->Bits.Length + sizeof(UINT32) - 1) / sizeof(UINT32));
|
||
|
|
bMsgLen++; //message header
|
||
|
|
while (1)
|
||
|
|
{
|
||
|
|
sHCsr.DWord = pMbarRegs->H_CSR;
|
||
|
|
sMeCsr.DWord = pMbarRegs->ME_CSR;
|
||
|
|
|
||
|
|
// If message is more than queue length go fail.
|
||
|
|
if (bMsgLen > sHCsr.Bits.H_CBD)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Send failed (msg %d B, queue %d B only)\n",
|
||
|
|
pThis->Fun, pMessage->Bits.Length, sHCsr.Bits.H_CBD * sizeof(UINT32));
|
||
|
|
Status = EFI_BAD_BUFFER_SIZE;
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
bEmptySlots = (UINT8)sHCsr.Bits.H_CBD -
|
||
|
|
(UINT8)((INT8)sHCsr.Bits.H_CBWP - (INT8)sHCsr.Bits.H_CBRP);
|
||
|
|
|
||
|
|
// Is it ready ?
|
||
|
|
if (!sMeCsr.Bits.ME_RDY || !sHCsr.Bits.H_RDY || bEmptySlots > sHCsr.Bits.H_CBD)
|
||
|
|
{
|
||
|
|
Status = HecClearQue(pThis, &Timeout);
|
||
|
|
if (EFI_ERROR(Status))
|
||
|
|
{
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (bMsgLen <= bEmptySlots)
|
||
|
|
{
|
||
|
|
for (i = 0; i < bMsgLen; i++)
|
||
|
|
{
|
||
|
|
pMbarRegs->CB_WW = ((UINT32*)pMessage)[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
sMeCsr.DWord = pMbarRegs->ME_CSR;
|
||
|
|
if (!sMeCsr.Bits.ME_RDY)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Queue has been reset while sending\n", pThis->Fun);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
sHCsr.DWord = pMbarRegs->H_CSR;
|
||
|
|
sHCsr.Bits.H_IS = 0;
|
||
|
|
sHCsr.Bits.H_IG = 1;
|
||
|
|
pMbarRegs->H_CSR = sHCsr.DWord;
|
||
|
|
Status = EFI_SUCCESS;
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
if (Timeout == 0)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Send failed (timeout)\n", pThis->Fun);
|
||
|
|
Status = EFI_TIMEOUT;
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
MicroSecondDelay(HECI_TIMEOUT_UNIT);
|
||
|
|
Timeout--;
|
||
|
|
}
|
||
|
|
GO_FAIL:
|
||
|
|
if (pTimeout != NULL)
|
||
|
|
{
|
||
|
|
*pTimeout = Timeout;
|
||
|
|
}
|
||
|
|
pThis->Mefs1.DWord = HeciPciReadMefs1();
|
||
|
|
iounmap((VOID *)pMbarRegs);
|
||
|
|
return Status;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
VOID *HeciMbarRead(HECI_DEVICE *pThis)
|
||
|
|
{
|
||
|
|
VOID *start;
|
||
|
|
|
||
|
|
UINT16 Cmd;
|
||
|
|
union
|
||
|
|
{
|
||
|
|
UINT64 QWord;
|
||
|
|
struct
|
||
|
|
{
|
||
|
|
UINT32 DWordL;
|
||
|
|
UINT32 DWordH;
|
||
|
|
} Bits;
|
||
|
|
} Mbar;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Read MBAR.
|
||
|
|
Mbar.QWord = 0;
|
||
|
|
Mbar.Bits.DWordL = PciRead32(pThis->PciCfg + HECI_REG_MBAR);
|
||
|
|
if (Mbar.Bits.DWordL == 0xFFFFFFFF)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] Device disabled\n", pThis->Fun);
|
||
|
|
Mbar.Bits.DWordL = 0;
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
if (Mbar.Bits.DWordL & 0x4) // if 64-bit address add the upper half
|
||
|
|
{
|
||
|
|
Mbar.Bits.DWordH = PciRead32(pThis->PciCfg + HECI_REG_MBAR + 4);
|
||
|
|
}
|
||
|
|
Mbar.Bits.DWordL &= 0xFFFFFFF0;
|
||
|
|
if (Mbar.QWord == 0)
|
||
|
|
{
|
||
|
|
if (pThis->Mbar == 0)
|
||
|
|
{
|
||
|
|
printk("[HECI-%d] MBAR not programmed\n", pThis->Fun);
|
||
|
|
goto GO_FAIL;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
Mbar.QWord = pThis->Mbar;
|
||
|
|
printk("[HECI-%d] MBAR not programmed, using default 0x%08X%08X\n",
|
||
|
|
pThis->Fun, Mbar.Bits.DWordH, Mbar.Bits.DWordL);
|
||
|
|
|
||
|
|
// Programm the MBAR, set the 64-bit support bit regardless of the size
|
||
|
|
// of the address currently used.
|
||
|
|
PciWrite32(pThis->PciCfg + HECI_REG_MBAR + 4, Mbar.Bits.DWordH);
|
||
|
|
PciWrite32(pThis->PciCfg + HECI_REG_MBAR, Mbar.Bits.DWordL | 4);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
pThis->Mbar = Mbar.QWord;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Enable the MBAR
|
||
|
|
Cmd = PciRead16(pThis->PciCfg + HECI_REG_COMMAND);
|
||
|
|
if (!(Cmd & HECI_CMD_MSE))
|
||
|
|
{
|
||
|
|
PciWrite16(pThis->PciCfg + HECI_REG_COMMAND, Cmd | HECI_CMD_BME | HECI_CMD_MSE);
|
||
|
|
}
|
||
|
|
GO_FAIL:
|
||
|
|
return (VOID*)(INTN)Mbar.QWord;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
VOID HeciTrace( HECI_DEVICE *pThis,
|
||
|
|
CHAR8 *pPrefix,
|
||
|
|
HECI_MSG_HEADER *pMsg,
|
||
|
|
INT32 MsgLen)
|
||
|
|
{
|
||
|
|
#if 0 /// Trace Enable or Disable
|
||
|
|
if (MsgLen > 4)
|
||
|
|
{
|
||
|
|
UINT32 dwLineBreak = 0;
|
||
|
|
UINT32 dwIndex = 0;
|
||
|
|
UINT8 *pMsgBody = (UINT8*)&pMsg[1];
|
||
|
|
|
||
|
|
MsgLen -= 4;
|
||
|
|
while (MsgLen-- > 0)
|
||
|
|
{
|
||
|
|
if (dwLineBreak == 0)
|
||
|
|
printk("%02x: ", (dwIndex & 0xF0));
|
||
|
|
printk("%02x ", pMsgBody[dwIndex++]);
|
||
|
|
dwLineBreak++;
|
||
|
|
if (dwLineBreak == 16)
|
||
|
|
{
|
||
|
|
printk("\n");
|
||
|
|
dwLineBreak = 0;
|
||
|
|
}
|
||
|
|
if (dwLineBreak == 8)
|
||
|
|
{
|
||
|
|
printk("-");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
printk("\n");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|