73 lines
2.8 KiB
Diff
73 lines
2.8 KiB
Diff
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From 96de5181b880adf2fd65fa85fbc3e0c74f976788 Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Wed, 1 Mar 2023 17:49:08 +0000
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Subject: [PATCH backport 5.10 5/6] platform: mellanox: Add field upgrade
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capability register
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Add new register to indicate the method of FPGA/CPLD field upgrade
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supported on the specific system.
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Currently two masks are available:
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b00 - field upgrade through LPC gateway (new method introduced to
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accelerate field upgrade process).
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b11 - field upgrade through CPU GPIO pins (old method).
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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Reviewed-by: Michael Shych <michaelsh@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index b5d51673f..f674d9173 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -66,6 +66,7 @@
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#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
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#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
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#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
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+#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
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#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
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@@ -241,6 +242,7 @@
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#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
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#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
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#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)
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+#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
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#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5)
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#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
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@@ -3956,6 +3958,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(5),
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.mode = 0200,
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},
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+ {
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+ .label = "jtag_cap",
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+ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
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+ .mask = MLXPLAT_CPLD_FU_CAP_MASK,
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+ .bit = 1,
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+ .mode = 0444,
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+ },
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{
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.label = "jtag_enable",
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.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
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@@ -5424,6 +5433,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
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@@ -5582,6 +5592,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
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--
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2.20.1
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