sonic-buildimage/platform/mellanox/non-upstream-patches/patches/0139-mlxsw-reg-Introduce-Management-Temperature-Extended-.patch

From a719653b2a7f0943e757c04dab73df324e469436 Mon Sep 17 00:00:00 2001
From: Vadim Pasternak <vadimp@nvidia.com>
Date: Wed, 12 May 2021 22:57:37 +0300
Subject: [PATCH] mlxsw: reg: Introduce Management Temperature Extended
 Capabilities Register

Introduce new register MTECR (Management Temperature Extended
Capabilities Register). This register exposes the capabilities of the
device and system temperature sensing. It provides information for
all possible temperature sensors that are on the system.

Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlxsw/reg.h | 67 +++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 89b21910f..c1ce0b42e 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -10297,6 +10297,72 @@ mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
 		*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
 }
 
+/* MTECR - Management Temperature Extended Capabilities Register
+ * -------------------------------------------------------------
+ * MTECR register exposes the capabilities of the device and system
+ * temperature sensing.
+ */
+#define MLXSW_REG_MTECR_ID 0x9109
+#define MLXSW_REG_MTECR_LEN 0x60
+#define MLXSW_REG_MTECR_SENSOR_MAP_LEN 0x58
+
+MLXSW_REG_DEFINE(mtecr, MLXSW_REG_MTECR_ID, MLXSW_REG_MTECR_LEN);
+
+/* reg_mtecr_last_sensor.
+ * Last sensor index that is available in the system to read from.
+ * Access: RO
+ */
+MLXSW_ITEM32(reg, mtecr, last_sensor, 0x00, 16, 12);
+
+/* reg_mtecr_sensor_count.
+ * Number of sensors supported by the device.
+ * This includes the ASIC, ambient sensors, Gearboxes etc.
+ * QSFP module sensors are not included.
+ * Access: RO
+ */
+MLXSW_ITEM32(reg, mtecr, sensor_count, 0x00, 0, 12);
+
+/* reg_mtecr_slot_index.
+ * Slot index (0: Main board).
+ * Access: Index
+ */
+MLXSW_ITEM32(reg, mtecr, slot_index, 0x04, 28, 4);
+
+/* reg_mtecr_internal_sensor_count.
+ * Number of sensors supported by the device that are in the ASIC.
+ * Access: RO
+ */
+MLXSW_ITEM32(reg, mtecr, internal_sensor_count, 0x04, 0, 7);
+
+/* reg_mtecr_sensor_map.
+ * Mapping of system sensors supported by the device. Each bit represents a
+ * sensor. This field is size variable based on the last_sensor field and in
+ * granularity of 32 bits.
+ * 0: Not connected or not supported
+ * 1: Supports temperature measurements
+ *
+ */
+MLXSW_ITEM_BIT_ARRAY(reg, mtecr, sensor_map, 0x08, MLXSW_REG_MTECR_SENSOR_MAP_LEN, 1);
+
+static inline void mlxsw_reg_mtecr_pack(char *payload, u8 slot_index)
+{
+	MLXSW_REG_ZERO(mtecr, payload);
+	mlxsw_reg_mtecr_slot_index_set(payload, slot_index);
+}
+
+static inline void mlxsw_reg_mtecr_unpack(char *payload, u16 *sensor_count,
+					  u16 *last_sensor,
+					  u8 *internal_sensor_count)
+{
+	if (sensor_count)
+		*sensor_count = mlxsw_reg_mtecr_sensor_count_get(payload);
+	if (last_sensor)
+		*last_sensor = mlxsw_reg_mtecr_last_sensor_get(payload);
+	if (internal_sensor_count)
+		*internal_sensor_count =
+			mlxsw_reg_mtecr_internal_sensor_count_get(payload);
+}
+
 /* MBCT - Management Binary Code Transfer Register
  * -----------------------------------------------
  * This register allows to transfer binary codes from the Host to
@@ -11884,6 +11950,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
 	MLXSW_REG(mtptpt),
 	MLXSW_REG(mfgd),
 	MLXSW_REG(mgpir),
+	MLXSW_REG(mtecr),
 	MLXSW_REG(mbct),
 	MLXSW_REG(mddq),
 	MLXSW_REG(mddc),
-- 
2.30.2