2020-08-06 05:16:11 -05:00
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/**
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@file dal.h
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@author Copyright (C) 2012 Centec Networks Inc. All rights reserved.
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@date 2012-4-9
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@version v2.0
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*/
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#ifndef _DAL_COMMON_H_
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#define _DAL_COMMON_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-05-01 12:37:07 -05:00
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#define DAL_MAX_CHIP_NUM 4 /* DAL support max chip num is 4 */
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2020-08-06 05:16:11 -05:00
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#define DAL_MAX_INTR_NUM 8
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#define DAL_NETIF_T_PORT 0
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#define DAL_NETIF_T_VLAN 1
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#define DAL_MAX_KNET_NETIF 64
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#define DAL_MAX_KNET_NAME_LEN 32
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2021-05-01 12:37:07 -05:00
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#define DAL_PCI_CMD_STATUS 0x0
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#define DAL_PCI_ADDR 0x4
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#define DAL_PCI_DATA_BUF 0x8
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2020-08-06 05:16:11 -05:00
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enum dal_operate_code_e
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{
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DAL_OP_CREATE,
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DAL_OP_DESTORY,
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DAL_OP_GET,
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DAL_OP_MAX,
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};
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typedef enum dal_operate_code_e dal_operate_code_t;
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struct dal_dma_info_s
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{
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unsigned int lchip;
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unsigned int phy_base;
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unsigned int phy_base_hi;
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unsigned int size;
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unsigned int knet_tx_offset;
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unsigned int knet_tx_size;
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unsigned int* virt_base;
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};
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typedef struct dal_dma_info_s dal_dma_info_t;
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2021-05-01 12:37:07 -05:00
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struct dal_dma_chan_s
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2020-08-06 05:16:11 -05:00
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{
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unsigned char lchip;
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unsigned char channel_id;
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unsigned char dmasel;
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unsigned char active;
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unsigned short current_index;
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unsigned short desc_num;
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unsigned short desc_depth;
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unsigned short data_size;
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unsigned long long mem_base;
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void* virt_base; /**< don't use when register chan*/
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unsigned char* p_desc_used; /**< don't use when register chan*/
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};
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typedef struct dal_dma_chan_s dal_dma_chan_t;
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struct dal_netif_s
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{
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unsigned char op_type;
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unsigned char netif_id;
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unsigned char type;
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unsigned char lchip;
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unsigned short vlan;
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unsigned int gport;
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unsigned char mac[6];
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char name[DAL_MAX_KNET_NAME_LEN];
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};
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typedef struct dal_netif_s dal_netif_t;
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/**
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@brief define dal error type
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*/
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enum dal_err_e
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{
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DAL_E_NONE = 0, /**< NO error */
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DAL_E_INVALID_PTR = -1000, /**< invalid pointer */
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DAL_E_INVALID_FD = -999, /**< invalid FD */
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DAL_E_TIME_OUT = -998, /**< time out */
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DAL_E_INVALID_ACCESS = -997, /**< invalid access type*/
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DAL_E_MPOOL_NOT_CREATE = -996, /**< mpool not create*/
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DAL_E_INVALID_IRQ = -995,
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DAL_E_DEV_NOT_FOUND = -994,
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DAL_E_EXCEED_MAX = -993,
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DAL_E_NOT_INIT = -992,
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DAL_E_ENVALID_MSI_PARA = -991,
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DAL_E_ERROR_CODE_END
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};
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enum dal_access_type_e
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{
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DAL_PCI_IO, /* [HB]humber is access as pci device, using ioctrl */
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DAL_SUPER_IF, /* [HB]humber is controled by fpga device */
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DAL_PCIE_MM, /* [GB]Gb is access as pcie device, using mmap */
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DAL_SPECIAL_EMU, /* [GB]special for emulation */
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DAL_MAX_ACCESS_TYPE
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};
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typedef enum dal_access_type_e dal_access_type_t;
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struct dal_pci_dev_s
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{
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unsigned int busNo;
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unsigned int devNo;
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unsigned int funNo;
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};
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typedef struct dal_pci_dev_s dal_pci_dev_t;
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2021-05-01 12:37:07 -05:00
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#ifndef HOST_IS_LE
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#define HOST_IS_LE 1
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#endif
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#if (HOST_IS_LE == 0)
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/* pci cmd struct define */
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typedef struct pci_cmd_status_s
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{
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unsigned int pcieReqOverlap : 1;
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unsigned int wrReqState : 3;
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unsigned int pciePoison : 1;
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unsigned int rcvregInProc : 1;
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unsigned int regInProc : 1;
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unsigned int reqProcAckCnt : 5;
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unsigned int reqProcAckError : 1;
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unsigned int reqProcTimeout : 1;
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unsigned int reqProcError : 1;
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unsigned int reqProcDone : 1;
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unsigned int pcieDataError : 1;
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unsigned int pcieReqError : 1;
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unsigned int reserved : 1;
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unsigned int cmdDataLen : 5;
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unsigned int cmdEntryWords : 4;
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unsigned int pcieReqCmdChk : 3;
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unsigned int cmdReadType : 1;
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} pci_cmd_status_t;
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#else
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typedef struct pci_cmd_status_s
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{
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unsigned int cmdReadType : 1; /* bit0 */
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unsigned int pcieReqCmdChk : 3; /* bit1~3 */
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unsigned int cmdEntryWords : 4; /* bit4~7 */
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unsigned int cmdDataLen : 5; /* bit8~12 */
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unsigned int reserved : 1; /* bit13 */
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unsigned int pcieReqError : 1;
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unsigned int pcieDataError : 1;
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unsigned int reqProcDone : 1;
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unsigned int reqProcError : 1;
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unsigned int reqProcTimeout : 1;
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unsigned int reqProcAckError : 1;
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unsigned int reqProcAckCnt : 5;
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unsigned int regInProc : 1;
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unsigned int rcvregInProc : 1;
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unsigned int pciePoison : 1;
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unsigned int wrReqState : 3;
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unsigned int pcieReqOverlap : 1;
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} pci_cmd_status_t;
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#endif
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typedef union pci_cmd_status_u_e
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{
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pci_cmd_status_t cmd_status;
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unsigned int val;
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} pci_cmd_status_u_t;
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2020-08-06 05:16:11 -05:00
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#ifdef __cplusplus
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}
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#endif
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#endif
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