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sonic-buildimage/device/arista/x86_64-arista_720dt_48s/td3x2-a720dt-48s-flex.config.bcm

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[Arista] Add initial support for 720DT-48S (#10656) Added initial set of config files to allow for booting and partial traffic testing in SONiC on the 720DT-48S. How to verify it - Switch boots - show interfaces status shows links up on interfaces Ethernet24-51 - Traffic flows with no errors on interfaces Ethernet24-51
2022-06-29 11:56:24 -05:00
PHY_AN_ALLOW_PLL_CHANGE=1
arl_clean_timeout_usec=15000000
asf_mem_profile.0=0
bcm_num_cos.0=9
bcm_stat_flags=1
bcm_stat_jumbo.0=9236
cdma_timeout_usec.0=15000000
disable_pcie_firmware_check.0=1
dma_desc_timeout_usec.0=15000000
fpem_mem_entries.0=0
higig2_hdr_mode.0=1
ifp_inports_support_enable.0=1
[Arista] Enable ipv6 128b lpm on 720DT-48S (#12832) Why I did it Added to allow test_crm_route to pass; the test tries to add a /126 ipv6 route and this change is required in order for the count of available routes to be updated correctly.
2022-11-28 21:20:50 -06:00
ipv6_lpm_128b_enable.0=1
[Arista] Add initial support for 720DT-48S (#10656) Added initial set of config files to allow for booting and partial traffic testing in SONiC on the 720DT-48S. How to verify it - Switch boots - show interfaces status shows links up on interfaces Ethernet24-51 - Traffic flows with no errors on interfaces Ethernet24-51
2022-06-29 11:56:24 -05:00
l2xmsg_mode.0=1
l2_mem_entries.0=65536
l3_mem_entries.0=32768
max_vp_lags.0=0
mem_scan_enable.0=1
miim_intr_enable.0=0
module_64ports.0=1
multicast_l2_range.0=4095
multicast_l3_range.0=0
os=unix
oversubscribe_mode=2
pbmp_xport_xe.0=0x1e1fffffffffffe
phy_an_c37_53.0=2
phy_an_c37_54.0=2
phy_an_c37_55.0=2
phy_an_c37_56.0=2
phy_an_c73_1.0=1
phy_an_c73_10.0=1
phy_an_c73_11.0=1
phy_an_c73_12.0=1
phy_an_c73_13.0=1
phy_an_c73_14.0=1
phy_an_c73_15.0=1
phy_an_c73_16.0=1
phy_an_c73_17.0=1
phy_an_c73_18.0=1
phy_an_c73_19.0=1
phy_an_c73_2.0=1
phy_an_c73_20.0=1
phy_an_c73_21.0=1
phy_an_c73_22.0=1
phy_an_c73_23.0=1
phy_an_c73_24.0=1
phy_an_c73_3.0=1
phy_an_c73_4.0=1
phy_an_c73_5.0=1
phy_an_c73_53.0=0
phy_an_c73_54.0=0
phy_an_c73_55.0=0
phy_an_c73_56.0=0
phy_an_c73_6.0=1
phy_an_c73_7.0=1
phy_an_c73_8.0=1
phy_an_c73_9.0=1
phy_chain_rx_lane_map_physical{1.0}=0x3210
phy_chain_rx_lane_map_physical{5.0}=0x3210
phy_chain_rx_lane_map_physical{9.0}=0x3210
phy_chain_rx_lane_map_physical{13.0}=0x3210
phy_chain_rx_lane_map_physical{17.0}=0x3210
phy_chain_rx_lane_map_physical{21.0}=0x3210
phy_chain_rx_lane_map_physical{25.0}=0x3210
phy_chain_rx_lane_map_physical{41.0}=0x3120
phy_chain_rx_lane_map_physical{61.0}=0x1032
phy_chain_rx_polarity_flip_physical{1.0}=0x0
phy_chain_rx_polarity_flip_physical{2.0}=0x0
phy_chain_rx_polarity_flip_physical{3.0}=0x0
phy_chain_rx_polarity_flip_physical{4.0}=0x0
phy_chain_rx_polarity_flip_physical{5.0}=0x0
phy_chain_rx_polarity_flip_physical{6.0}=0x0
phy_chain_rx_polarity_flip_physical{7.0}=0x0
phy_chain_rx_polarity_flip_physical{8.0}=0x0
phy_chain_rx_polarity_flip_physical{9.0}=0x0
phy_chain_rx_polarity_flip_physical{10.0}=0x0
phy_chain_rx_polarity_flip_physical{11.0}=0x0
phy_chain_rx_polarity_flip_physical{12.0}=0x0
phy_chain_rx_polarity_flip_physical{13.0}=0x0
phy_chain_rx_polarity_flip_physical{14.0}=0x0
phy_chain_rx_polarity_flip_physical{15.0}=0x0
phy_chain_rx_polarity_flip_physical{16.0}=0x0
phy_chain_rx_polarity_flip_physical{17.0}=0x0
phy_chain_rx_polarity_flip_physical{18.0}=0x0
phy_chain_rx_polarity_flip_physical{19.0}=0x0
phy_chain_rx_polarity_flip_physical{20.0}=0x0
phy_chain_rx_polarity_flip_physical{21.0}=0x0
phy_chain_rx_polarity_flip_physical{22.0}=0x0
phy_chain_rx_polarity_flip_physical{23.0}=0x0
phy_chain_rx_polarity_flip_physical{24.0}=0x0
phy_chain_rx_polarity_flip_physical{25.0}=0x0
phy_chain_rx_polarity_flip_physical{29.0}=0x0
phy_chain_rx_polarity_flip_physical{33.0}=0x0
phy_chain_rx_polarity_flip_physical{37.0}=0x0
phy_chain_rx_polarity_flip_physical{41.0}=0x0
phy_chain_rx_polarity_flip_physical{45.0}=0x0
phy_chain_rx_polarity_flip_physical{61.0}=0x0
phy_chain_rx_polarity_flip_physical{62.0}=0x0
phy_chain_rx_polarity_flip_physical{63.0}=0x0
phy_chain_rx_polarity_flip_physical{64.0}=0x0
phy_chain_tx_lane_map_physical{1.0}=0x3210
phy_chain_tx_lane_map_physical{5.0}=0x3210
phy_chain_tx_lane_map_physical{9.0}=0x3210
phy_chain_tx_lane_map_physical{13.0}=0x3210
phy_chain_tx_lane_map_physical{17.0}=0x3210
phy_chain_tx_lane_map_physical{21.0}=0x3210
phy_chain_tx_lane_map_physical{25.0}=0x3210
phy_chain_tx_lane_map_physical{41.0}=0x3120
phy_chain_tx_lane_map_physical{61.0}=0x1032
phy_chain_tx_polarity_flip_physical{1.0}=0x0
phy_chain_tx_polarity_flip_physical{2.0}=0x0
phy_chain_tx_polarity_flip_physical{3.0}=0x0
phy_chain_tx_polarity_flip_physical{4.0}=0x0
phy_chain_tx_polarity_flip_physical{5.0}=0x0
phy_chain_tx_polarity_flip_physical{6.0}=0x0
phy_chain_tx_polarity_flip_physical{7.0}=0x0
phy_chain_tx_polarity_flip_physical{8.0}=0x0
phy_chain_tx_polarity_flip_physical{9.0}=0x0
phy_chain_tx_polarity_flip_physical{10.0}=0x0
phy_chain_tx_polarity_flip_physical{11.0}=0x0
phy_chain_tx_polarity_flip_physical{12.0}=0x0
phy_chain_tx_polarity_flip_physical{13.0}=0x0
phy_chain_tx_polarity_flip_physical{14.0}=0x0
phy_chain_tx_polarity_flip_physical{15.0}=0x0
phy_chain_tx_polarity_flip_physical{16.0}=0x0
phy_chain_tx_polarity_flip_physical{17.0}=0x0
phy_chain_tx_polarity_flip_physical{18.0}=0x0
phy_chain_tx_polarity_flip_physical{19.0}=0x0
phy_chain_tx_polarity_flip_physical{20.0}=0x0
phy_chain_tx_polarity_flip_physical{21.0}=0x0
phy_chain_tx_polarity_flip_physical{22.0}=0x0
phy_chain_tx_polarity_flip_physical{23.0}=0x0
phy_chain_tx_polarity_flip_physical{24.0}=0x0
phy_chain_tx_polarity_flip_physical{25.0}=0x0
phy_chain_tx_polarity_flip_physical{29.0}=0x0
phy_chain_tx_polarity_flip_physical{33.0}=0x0
phy_chain_tx_polarity_flip_physical{37.0}=0x0
phy_chain_tx_polarity_flip_physical{41.0}=0x0
phy_chain_tx_polarity_flip_physical{45.0}=0x0
phy_chain_tx_polarity_flip_physical{61.0}=0x0
phy_chain_tx_polarity_flip_physical{62.0}=0x0
phy_chain_tx_polarity_flip_physical{63.0}=0x0
phy_chain_tx_polarity_flip_physical{64.0}=0x0
phy_port_primary_and_offset_25=0x0100
phy_port_primary_and_offset_26=0x0101
phy_port_primary_and_offset_27=0x0102
phy_port_primary_and_offset_28=0x0103
phy_port_primary_and_offset_29=0x0104
phy_port_primary_and_offset_30=0x0105
phy_port_primary_and_offset_31=0x0106
phy_port_primary_and_offset_32=0x0107
phy_port_primary_and_offset_33=0x0900
phy_port_primary_and_offset_34=0x0901
phy_port_primary_and_offset_35=0x0902
phy_port_primary_and_offset_36=0x0903
phy_port_primary_and_offset_37=0x0904
phy_port_primary_and_offset_38=0x0905
phy_port_primary_and_offset_39=0x0906
phy_port_primary_and_offset_40=0x0907
phy_port_primary_and_offset_41=0x1100
phy_port_primary_and_offset_42=0x1101
phy_port_primary_and_offset_43=0x1102
phy_port_primary_and_offset_44=0x1103
phy_port_primary_and_offset_45=0x1104
phy_port_primary_and_offset_46=0x1105
phy_port_primary_and_offset_47=0x1106
phy_port_primary_and_offset_48=0x1107
portmap_1.0=25:1
portmap_2.0=26:1
portmap_3.0=27:1
portmap_4.0=28:1
portmap_5.0=29:1
portmap_6.0=30:1
portmap_7.0=31:1
portmap_8.0=32:1
portmap_9.0=33:1
portmap_10.0=34:1
portmap_11.0=35:1
portmap_12.0=36:1
portmap_13.0=37:1
portmap_14.0=38:1
portmap_15.0=39:1
portmap_16.0=40:1
portmap_17.0=41:1
portmap_18.0=42:1
portmap_19.0=43:1
portmap_20.0=44:1
portmap_21.0=45:1
portmap_22.0=46:1
portmap_23.0=47:1
portmap_24.0=48:1
portmap_25.0=1:1
portmap_26.0=2:1
portmap_27.0=3:1
portmap_28.0=4:1
portmap_29.0=5:1
portmap_30.0=6:1
portmap_31.0=7:1
portmap_32.0=8:1
portmap_33.0=9:1
portmap_34.0=10:1
portmap_35.0=11:1
portmap_36.0=12:1
portmap_37.0=13:1
portmap_38.0=14:1
portmap_39.0=15:1
portmap_40.0=16:1
portmap_41.0=17:1
portmap_42.0=18:1
portmap_43.0=19:1
portmap_44.0=20:1
portmap_45.0=21:1
portmap_46.0=22:1
portmap_47.0=23:1
portmap_48.0=24:1
portmap_53.0=61:10
portmap_54.0=62:10
portmap_55.0=63:10
portmap_56.0=64:10
port_flex_enable.0=1
port_gmii_mode{25}=1
port_gmii_mode{41}=1
[Arista] Add missing configs for 720DT-48S (#11362) * Why I did it Followup to #10656. This change adds the remaining configs for the 720DT-48S platform. * How I did it Adds the following: gearbox_config.json and other gearbox-related config files, to enable traffic on external PHY ports (Ethernet0-23) sensors.conf pcie.yaml Also add missing facts in platform.json * How to verify it show interfaces status shows links up on interfaces Ethernet0-23 traffic flows with no errors on interfaces Ethernet0-23 Note: above testing depends on Add gbsyncd container for broncos #11154 and [orchagent]: Enhance initSaiPhyApi sonic-swss#2367, as well as having the appropriate PAI driver. Co-authored-by: Samuel Angebault <staphylo@arista.com>
2022-07-19 22:36:16 -05:00
port_init_autoneg_1.0=1
port_init_autoneg_2.0=1
port_init_autoneg_3.0=1
port_init_autoneg_4.0=1
port_init_autoneg_5.0=1
port_init_autoneg_6.0=1
port_init_autoneg_7.0=1
port_init_autoneg_8.0=1
port_init_autoneg_9.0=1
port_init_autoneg_10.0=1
port_init_autoneg_11.0=1
port_init_autoneg_12.0=1
port_init_autoneg_13.0=1
port_init_autoneg_14.0=1
port_init_autoneg_15.0=1
port_init_autoneg_16.0=1
port_init_autoneg_17.0=1
port_init_autoneg_18.0=1
port_init_autoneg_19.0=1
port_init_autoneg_20.0=1
port_init_autoneg_21.0=1
port_init_autoneg_22.0=1
port_init_autoneg_23.0=1
port_init_autoneg_24.0=1
[Arista] Add initial support for 720DT-48S (#10656) Added initial set of config files to allow for booting and partial traffic testing in SONiC on the 720DT-48S. How to verify it - Switch boots - show interfaces status shows links up on interfaces Ethernet24-51 - Traffic flows with no errors on interfaces Ethernet24-51
2022-06-29 11:56:24 -05:00
port_init_autoneg_53.0=0
port_init_autoneg_54.0=0
port_init_autoneg_55.0=0
port_init_autoneg_56.0=0
port_phy_addr_1.0=0xff
port_phy_addr_2.0=0xff
port_phy_addr_3.0=0xff
port_phy_addr_4.0=0xff
port_phy_addr_5.0=0xff
port_phy_addr_6.0=0xff
port_phy_addr_7.0=0xff
port_phy_addr_8.0=0xff
port_phy_addr_9.0=0xff
port_phy_addr_10.0=0xff
port_phy_addr_11.0=0xff
port_phy_addr_12.0=0xff
port_phy_addr_13.0=0xff
port_phy_addr_14.0=0xff
port_phy_addr_15.0=0xff
port_phy_addr_16.0=0xff
port_phy_addr_17.0=0xff
port_phy_addr_18.0=0xff
port_phy_addr_19.0=0xff
port_phy_addr_20.0=0xff
port_phy_addr_21.0=0xff
port_phy_addr_22.0=0xff
port_phy_addr_23.0=0xff
port_phy_addr_24.0=0xff
port_phy_addr_53.0=0xff
port_phy_addr_54.0=0xff
port_phy_addr_55.0=0xff
port_phy_addr_56.0=0xff
robust_hash_disable_egress_vlan.0=1
robust_hash_disable_mpls.0=1
robust_hash_disable_vlan.0=1
serdes_core_rx_polarity_flip_physical{1}=0x0
serdes_core_rx_polarity_flip_physical{5}=0x0
serdes_core_rx_polarity_flip_physical{9}=0x0
serdes_core_rx_polarity_flip_physical{13}=0x0
serdes_core_rx_polarity_flip_physical{17}=0x0
serdes_core_rx_polarity_flip_physical{21}=0x0
serdes_core_rx_polarity_flip_physical{25}=0x0
serdes_core_rx_polarity_flip_physical{41}=0x0
serdes_core_rx_polarity_flip_physical{61}=0x0
serdes_core_tx_polarity_flip_physical{1}=0x0
serdes_core_tx_polarity_flip_physical{5}=0x0
serdes_core_tx_polarity_flip_physical{9}=0x0
serdes_core_tx_polarity_flip_physical{13}=0x0
serdes_core_tx_polarity_flip_physical{17}=0x0
serdes_core_tx_polarity_flip_physical{21}=0x0
serdes_core_tx_polarity_flip_physical{25}=0x0
serdes_core_tx_polarity_flip_physical{41}=0x0
serdes_core_tx_polarity_flip_physical{61}=0x0
sram_scan_enable.0=0
stable_size=0x5500000
tdma_timeout_usec.0=15000000
tslam_timeout_usec.0=15000000
[arista]: Add sai_mdio_access_clause22=1 in td3x2-a720dt-48s-flex.config.bcm (#11303) Add sai_mdio_access_clause22=1 in td3x2-a720dt-48s-flex.config.bcm Signed-off-by: Jiahua Wang <jiahua.wang@broadcom.com>
2022-07-27 12:04:40 -05:00
sai_mdio_access_clause22=1
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