637 lines
15 KiB
C
637 lines
15 KiB
C
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#include "i2c-mei_rw.h"
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/* ========== IoLibGcc.c ========= */
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/**
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Reads an 8-bit I/O port.
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Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
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This function must guarantee that all I/O read and write operations are
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serialized.
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If 8-bit I/O port operations are not supported, then ASSERT().
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@param Port The I/O port to read.
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@return The value read.
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**/
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//__inline__
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UINT8
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IoRead8 (
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IN UINTN Port
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)
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{
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UINT8 Data;
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__asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));
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return Data;
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}
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/**
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Writes an 8-bit I/O port.
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Writes the 8-bit I/O port specified by Port with the value specified by Value
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and returns Value. This function must guarantee that all I/O read and write
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operations are serialized.
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If 8-bit I/O port operations are not supported, then ASSERT().
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@param Port The I/O port to write.
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@param Value The value to write to the I/O port.
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@return The value written the I/O port.
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**/
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//__inline__
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UINT8
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IoWrite8 (
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IN UINTN Port,
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IN UINT8 Value
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)
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{
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__asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));
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return Value;;
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}
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/**
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Reads a 16-bit I/O port.
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Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
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This function must guarantee that all I/O read and write operations are
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serialized.
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If 16-bit I/O port operations are not supported, then ASSERT().
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If Port is not aligned on a 16-bit boundary, then ASSERT().
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@param Port The I/O port to read.
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@return The value read.
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**/
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//__inline__
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UINT16
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IoRead16 (
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IN UINTN Port
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)
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{
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UINT16 Data;
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if((Port & 1) != 0)
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printk("Failed\n");
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__asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));
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return Data;
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}
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/**
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Writes a 16-bit I/O port.
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Writes the 16-bit I/O port specified by Port with the value specified by Value
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and returns Value. This function must guarantee that all I/O read and write
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operations are serialized.
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If 16-bit I/O port operations are not supported, then ASSERT().
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If Port is not aligned on a 16-bit boundary, then ASSERT().
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@param Port The I/O port to write.
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@param Value The value to write to the I/O port.
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@return The value written the I/O port.
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**/
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//__inline__
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UINT16
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IoWrite16 (
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IN UINTN Port,
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IN UINT16 Value
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)
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{
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if((Port & 1) != 0)
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printk("Failed\n");
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__asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));
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return Value;;
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}
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/**
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Reads a 32-bit I/O port.
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Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
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This function must guarantee that all I/O read and write operations are
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serialized.
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If 32-bit I/O port operations are not supported, then ASSERT().
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If Port is not aligned on a 32-bit boundary, then ASSERT().
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@param Port The I/O port to read.
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@return The value read.
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**/
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//__inline__
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UINT32
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IoRead32 (
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IN UINTN Port
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)
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{
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UINT32 Data;
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if((Port & 3) != 0)
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printk("Failed\n");
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__asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));
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return Data;
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}
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/**
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Writes a 32-bit I/O port.
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Writes the 32-bit I/O port specified by Port with the value specified by Value
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and returns Value. This function must guarantee that all I/O read and write
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operations are serialized.
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If 32-bit I/O port operations are not supported, then ASSERT().
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If Port is not aligned on a 32-bit boundary, then ASSERT().
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@param Port The I/O port to write.
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@param Value The value to write to the I/O port.
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@return The value written the I/O port.
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**/
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//__inline__
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UINT32
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IoWrite32 (
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IN UINTN Port,
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IN UINT32 Value
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)
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{
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if((Port & 3) != 0)
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printk("Failed\n");
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__asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));
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return Value;
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}
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/* ========== GccInline.c ========= */
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/**
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Enables CPU interrupts.
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Enables CPU interrupts.
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**/
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VOID
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EnableInterrupts (
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VOID
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)
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{
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__asm__ __volatile__ ("sti"::: "memory");
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}
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/**
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Disables CPU interrupts.
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Disables CPU interrupts.
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**/
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VOID
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DisableInterrupts (
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VOID
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)
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{
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__asm__ __volatile__ ("cli"::: "memory");
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}
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/**
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Reads the current value of the EFLAGS register.
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Reads and returns the current value of the EFLAGS register. This function is
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only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
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64-bit value on X64.
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@return EFLAGS on IA-32 or RFLAGS on X64.
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**/
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UINTN
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AsmReadEflags (
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VOID
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)
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{
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UINTN Eflags;
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__asm__ __volatile__ (
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"pushfq \n\t"
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"pop %0 "
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: "=r" (Eflags) // %0
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);
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return Eflags;
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}
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/* ========== X86GetInterruptState.c ========= */
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/**
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Retrieves the current CPU interrupt state.
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Returns TRUE is interrupts are currently enabled. Otherwise
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returns FALSE.
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@retval TRUE CPU interrupts are enabled.
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@retval FALSE CPU interrupts are disabled.
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**/
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BOOLEAN
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GetInterruptState (
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VOID
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)
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{
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IA32_EFLAGS32 EFlags;
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EFlags.UintN = AsmReadEflags ();
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return (BOOLEAN)(1 == EFlags.Bits.IF);
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}
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/* ========== Cpu.c ========= */
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/**
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Disables CPU interrupts and returns the interrupt state prior to the disable
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operation.
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@retval TRUE CPU interrupts were enabled on entry to this call.
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@retval FALSE CPU interrupts were disabled on entry to this call.
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**/
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BOOLEAN
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SaveAndDisableInterrupts (
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VOID
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)
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{
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BOOLEAN InterruptState;
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InterruptState = GetInterruptState ();
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DisableInterrupts ();
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return InterruptState;
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}
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/**
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Set the current CPU interrupt state.
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Sets the current CPU interrupt state to the state specified by
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InterruptState. If InterruptState is TRUE, then interrupts are enabled. If
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InterruptState is FALSE, then interrupts are disabled. InterruptState is
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returned.
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@param InterruptState TRUE if interrupts should be enabled. FALSE if
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interrupts should be disabled.
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@return InterruptState
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**/
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BOOLEAN
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SetInterruptState (
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IN BOOLEAN InterruptState
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)
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{
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if (InterruptState) {
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EnableInterrupts ();
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} else {
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DisableInterrupts ();
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}
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return InterruptState;
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}
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/* ========== pciLib.c ========= */
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//
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// Declare I/O Ports used to perform PCI Confguration Cycles
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//
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#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8
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#define PCI_CONFIGURATION_DATA_PORT 0xCFC
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/**
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Convert a PCI Library address to PCI CF8 formatted address.
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Declare macro to convert PCI Library address to PCI CF8 formatted address.
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Bit fields of PCI Library and CF8 formatted address is as follows:
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PCI Library formatted address CF8 Formatted Address
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============================= ======================
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Bits 00..11 Register Bits 00..07 Register
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Bits 12..14 Function Bits 08..10 Function
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Bits 15..19 Device Bits 11..15 Device
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Bits 20..27 Bus Bits 16..23 Bus
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Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)
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Bits 31..31 Must be 1
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@param A The address to convert.
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@retval The coverted address.
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**/
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#define PCI_TO_CF8_ADDRESS(A) \
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((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))
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/**
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Reads an 8-bit PCI configuration register.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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If the register specified by Address >= 0x100, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@return The read value from the PCI configuration register.
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**/
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UINT8
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PciCf8Read8 (
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IN UINTN Address
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)
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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Result = IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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/**
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Writes an 8-bit PCI configuration register.
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Writes the 8-bit PCI configuration register specified by Address with the
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value specified by Value. Value is returned. This function must guarantee
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that all PCI read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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If the register specified by Address >= 0x100, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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PciCf8Write8 (
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IN UINTN Address,
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IN UINT8 Value
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)
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{
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BOOLEAN InterruptState;
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UINT32 AddressPort;
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UINT8 Result;
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InterruptState = SaveAndDisableInterrupts ();
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AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
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Result = IoWrite8 (
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PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
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Value
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);
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IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
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SetInterruptState (InterruptState);
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return Result;
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}
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/**
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Reads a 16-bit PCI configuration register.
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Reads and returns the 16-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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If Address is not aligned on a 16-bit boundary, then ASSERT().
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If the register specified by Address >= 0x100, then ASSERT().
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|
|
|
||
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||
|
|
Register.
|
||
|
|
|
||
|
|
@return The read value from the PCI configuration register.
|
||
|
|
|
||
|
|
**/
|
||
|
|
UINT16
|
||
|
|
PciCf8Read16 (
|
||
|
|
IN UINTN Address
|
||
|
|
)
|
||
|
|
{
|
||
|
|
BOOLEAN InterruptState;
|
||
|
|
UINT32 AddressPort;
|
||
|
|
UINT16 Result;
|
||
|
|
|
||
|
|
InterruptState = SaveAndDisableInterrupts ();
|
||
|
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||
|
|
Result = IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||
|
|
SetInterruptState (InterruptState);
|
||
|
|
return Result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
Writes a 16-bit PCI configuration register.
|
||
|
|
|
||
|
|
Writes the 16-bit PCI configuration register specified by Address with the
|
||
|
|
value specified by Value. Value is returned. This function must guarantee
|
||
|
|
that all PCI read and write operations are serialized.
|
||
|
|
|
||
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
||
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
||
|
|
If the register specified by Address >= 0x100, then ASSERT().
|
||
|
|
|
||
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||
|
|
Register.
|
||
|
|
@param Value The value to write.
|
||
|
|
|
||
|
|
@return The value written to the PCI configuration register.
|
||
|
|
|
||
|
|
**/
|
||
|
|
UINT16
|
||
|
|
PciCf8Write16 (
|
||
|
|
IN UINTN Address,
|
||
|
|
IN UINT16 Value
|
||
|
|
)
|
||
|
|
{
|
||
|
|
BOOLEAN InterruptState;
|
||
|
|
UINT32 AddressPort;
|
||
|
|
UINT16 Result;
|
||
|
|
|
||
|
|
InterruptState = SaveAndDisableInterrupts ();
|
||
|
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||
|
|
Result = IoWrite16 (
|
||
|
|
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
|
||
|
|
Value
|
||
|
|
);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||
|
|
SetInterruptState (InterruptState);
|
||
|
|
return Result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
Reads a 32-bit PCI configuration register.
|
||
|
|
|
||
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
||
|
|
This function must guarantee that all PCI read and write operations are
|
||
|
|
serialized.
|
||
|
|
|
||
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
||
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||
|
|
If the register specified by Address >= 0x100, then ASSERT().
|
||
|
|
|
||
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||
|
|
Register.
|
||
|
|
|
||
|
|
@return The read value from the PCI configuration register.
|
||
|
|
|
||
|
|
**/
|
||
|
|
UINT32
|
||
|
|
PciCf8Read32 (
|
||
|
|
IN UINTN Address
|
||
|
|
)
|
||
|
|
{
|
||
|
|
BOOLEAN InterruptState;
|
||
|
|
UINT32 AddressPort;
|
||
|
|
UINT32 Result;
|
||
|
|
|
||
|
|
InterruptState = SaveAndDisableInterrupts ();
|
||
|
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||
|
|
Result = IoRead32 (PCI_CONFIGURATION_DATA_PORT);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||
|
|
SetInterruptState (InterruptState);
|
||
|
|
return Result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
Writes a 32-bit PCI configuration register.
|
||
|
|
|
||
|
|
Writes the 32-bit PCI configuration register specified by Address with the
|
||
|
|
value specified by Value. Value is returned. This function must guarantee
|
||
|
|
that all PCI read and write operations are serialized.
|
||
|
|
|
||
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
||
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
||
|
|
If the register specified by Address >= 0x100, then ASSERT().
|
||
|
|
|
||
|
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||
|
|
Register.
|
||
|
|
@param Value The value to write.
|
||
|
|
|
||
|
|
@return The value written to the PCI configuration register.
|
||
|
|
|
||
|
|
**/
|
||
|
|
UINT32
|
||
|
|
PciCf8Write32 (
|
||
|
|
IN UINTN Address,
|
||
|
|
IN UINT32 Value
|
||
|
|
)
|
||
|
|
{
|
||
|
|
BOOLEAN InterruptState;
|
||
|
|
UINT32 AddressPort;
|
||
|
|
UINT32 Result;
|
||
|
|
|
||
|
|
InterruptState = SaveAndDisableInterrupts ();
|
||
|
|
AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
|
||
|
|
Result = IoWrite32 (
|
||
|
|
PCI_CONFIGURATION_DATA_PORT,
|
||
|
|
Value
|
||
|
|
);
|
||
|
|
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);
|
||
|
|
SetInterruptState (InterruptState);
|
||
|
|
return Result;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/* ========== Other ========= */
|
||
|
|
|
||
|
|
// UINT8 PciRead8(UINT64 addr)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X.\n", __func__, addr);
|
||
|
|
// return 0x01;
|
||
|
|
// }
|
||
|
|
|
||
|
|
// UINT8 PciWrite8(UINT64 addr, UINT8 data)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X data: %2X.\n", __func__, addr, data);
|
||
|
|
// return 0x02;
|
||
|
|
// }
|
||
|
|
|
||
|
|
|
||
|
|
// UINT16 PciRead16(UINT64 addr)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X.\n", __func__, addr);
|
||
|
|
// return 0x03;
|
||
|
|
// }
|
||
|
|
|
||
|
|
// UINT16 PciWrite16(UINT64 addr, UINT8 data)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X data: %2X.\n", __func__, addr, data);
|
||
|
|
// return 0x04;
|
||
|
|
// }
|
||
|
|
|
||
|
|
|
||
|
|
// UINT32 PciRead32(UINT64 addr)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X.\n", __func__, addr);
|
||
|
|
// return 0x05;
|
||
|
|
// }
|
||
|
|
|
||
|
|
// UINT32 PciWrite32(UINT64 addr, UINT8 data)
|
||
|
|
// {
|
||
|
|
// printf("[%s] addr: %8X data: %2X.\n", __func__, addr, data);
|
||
|
|
// return 0x06;
|
||
|
|
// }
|
||
|
|
|
||
|
|
UINT8 PciRead8(UINT64 addr)
|
||
|
|
{
|
||
|
|
return PciCf8Read8 (addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT8 PciWrite8(UINT64 addr, UINT8 data)
|
||
|
|
{
|
||
|
|
return PciCf8Write8 (addr, data);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
UINT16 PciRead16(UINT64 addr)
|
||
|
|
{
|
||
|
|
return PciCf8Read16 (addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT16 PciWrite16(UINT64 addr, UINT8 data)
|
||
|
|
{
|
||
|
|
return PciCf8Write16 (addr, data);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
UINT32 PciRead32(UINT64 addr)
|
||
|
|
{
|
||
|
|
return PciCf8Read32 (addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT32 PciWrite32(UINT64 addr, UINT8 data)
|
||
|
|
{
|
||
|
|
return PciCf8Write32 (addr, data);
|
||
|
|
}
|