448 lines
11 KiB
C
448 lines
11 KiB
C
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/*
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* cls_switchboard.c - PCI device driver for Silverstone Switch board FPGA.
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*
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* Author: Pradchaya Phucharoen
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*
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* Copyright (C) 2019 Celestica Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/i2c/pca954x.h>
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#include "cls-i2c-ocore.h"
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#define MOD_VERSION "2.1.0-1"
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#define DRV_NAME "cls-switchboard"
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#define I2C_MUX_CHANNEL(_ch, _adap_id, _deselect) \
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[_ch] = { .adap_id = _adap_id, .deselect_on_exit = _deselect }
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#define FPGA_PCIE_DEVICE_ID 0x7021
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#define MMIO_BAR 0
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#define I2C_BUS_OFS 9
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/* I2C ocore configurations */
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#define OCORE_REGSHIFT 2
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#define OCORE_IP_CLK_khz 62500 //TODO: check fpga's `wb_clk_i`
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#define OCORE_BUS_CLK_khz 100
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#define OCORE_REG_IO_WIDTH 1
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/* Optical port xcvr configuration */
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#define XCVR_REG_SHIFT 2
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#define XCVR_NUM_PORT 34
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#define XCVR_PORT_REG_SIZE 0x10
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/* i2c_bus_config - an i2c-core resource and platform data
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* @id - I2C bus device ID, for identification.
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* @res - resources for an i2c-core device.
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* @num_res - size of the resources.
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* @pdata - a platform data of an i2c-core device.
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*/
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struct i2c_bus_config {
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int id;
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struct resource *res;
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ssize_t num_res;
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struct ocores_i2c_platform_data pdata;
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};
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/* switchbrd_priv - switchboard private data */
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struct switchbrd_priv {
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unsigned long base;
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int num_i2c_bus;
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struct platform_device **i2cbuses_pdev;
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struct platform_device *regio_pdev;
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struct platform_device *spiflash_pdev;
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//struct platform_device *xcvr_pdev;
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};
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// NOTE: Silverstone i2c channel mapping is very wierd!!!
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/* PCA9548 channel config on MASTER BUS 3 */
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static struct pca954x_platform_mode i2c_mux_70_modes[] = {
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 23, true),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 26, true),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 27, true),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 28, true),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 29, true),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 30, true),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 31, true),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 32, true),
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};
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static struct pca954x_platform_mode i2c_mux_71_modes[] = {
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 1, true),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 2, true),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 3, true),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 4, true),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 5, true),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 6, true),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 15, true),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 8, true),
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};
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static struct pca954x_platform_mode i2c_mux_72_modes[] = {
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 17, true),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 18, true),
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 19, true),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 20, true),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 21, true),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 22, true),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 25, true),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 24, true),
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};
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static struct pca954x_platform_mode i2c_mux_73_modes[] = {
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I2C_MUX_CHANNEL(4, I2C_BUS_OFS + 9, true),
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I2C_MUX_CHANNEL(3, I2C_BUS_OFS + 10, true),
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I2C_MUX_CHANNEL(6, I2C_BUS_OFS + 11, true),
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I2C_MUX_CHANNEL(2, I2C_BUS_OFS + 12, true),
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I2C_MUX_CHANNEL(1, I2C_BUS_OFS + 13, true),
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I2C_MUX_CHANNEL(5, I2C_BUS_OFS + 14, true),
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I2C_MUX_CHANNEL(7, I2C_BUS_OFS + 7, true),
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I2C_MUX_CHANNEL(0, I2C_BUS_OFS + 16, true),
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};
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static struct pca954x_platform_data om_muxes[] = {
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{
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.modes = i2c_mux_70_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_70_modes),
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},
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{
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.modes = i2c_mux_71_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_71_modes),
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},
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{
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.modes = i2c_mux_72_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_72_modes),
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},
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{
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.modes = i2c_mux_73_modes,
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.num_modes = ARRAY_SIZE(i2c_mux_73_modes),
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},
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};
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/* Optical Module bus 3 i2c muxes info */
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static struct i2c_board_info i2c_info_3[] = {
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{
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I2C_BOARD_INFO("pca9548", 0x70),
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.platform_data = &om_muxes[0],
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},
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{
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I2C_BOARD_INFO("pca9548", 0x71),
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.platform_data = &om_muxes[1],
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},
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{
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I2C_BOARD_INFO("pca9548", 0x72),
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.platform_data = &om_muxes[2],
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},
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{
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I2C_BOARD_INFO("pca9548", 0x73),
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.platform_data = &om_muxes[3],
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},
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};
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/* RESOURCE SEPERATES BY FUNCTION */
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/* Resource IOMEM for i2c bus 1 */
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static struct resource cls_i2c_res_1[] = {
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{
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.start = 0x800, .end = 0x81F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 2 */
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static struct resource cls_i2c_res_2[] = {
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{
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.start = 0x820, .end = 0x83F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 3 */
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static struct resource cls_i2c_res_3[] = {
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{
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.start = 0x840, .end = 0x85F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 4 */
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static struct resource cls_i2c_res_4[] = {
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{
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.start = 0x860, .end = 0x87F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for i2c bus 5 */
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static struct resource cls_i2c_res_5[] = {
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{
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.start = 0x880, .end = 0x89F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for reg access */
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static struct resource reg_io_res[] = {
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{
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.start = 0x00, .end = 0xFF,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for spi flash firmware upgrade */
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static struct resource spi_flash_res[] = {
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{
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.start = 0x1200, .end = 0x121F,
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.flags = IORESOURCE_MEM,},
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};
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/* Resource IOMEM for front panel XCVR */
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// static struct resource xcvr_res[] = {
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// {
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// .start = 0x4000, .end = 0x421F,
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// .flags = IORESOURCE_MEM,},
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// };
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static struct i2c_bus_config i2c_bus_configs[] = {
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{
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.id = 1,
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.res = cls_i2c_res_1,
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.num_res = ARRAY_SIZE(cls_i2c_res_1),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 2,
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.res = cls_i2c_res_2,
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.num_res = ARRAY_SIZE(cls_i2c_res_2),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 3,
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.res = cls_i2c_res_3,
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.num_res = ARRAY_SIZE(cls_i2c_res_3),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = ARRAY_SIZE(i2c_info_3),
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.devices = i2c_info_3,
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},
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},
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{
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.id = 4,
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.res = cls_i2c_res_4,
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.num_res = ARRAY_SIZE(cls_i2c_res_4),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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{
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.id = 5,
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.res = cls_i2c_res_5,
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.num_res = ARRAY_SIZE(cls_i2c_res_5),
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.pdata = {
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.reg_shift = OCORE_REGSHIFT,
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.reg_io_width = OCORE_REG_IO_WIDTH,
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.clock_khz = OCORE_IP_CLK_khz,
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.bus_khz = OCORE_BUS_CLK_khz,
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.big_endian = false,
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.num_devices = 0,
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.devices = NULL,
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},
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},
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};
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// TODO: Add a platform configuration struct, and use probe as a factory,
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// so xcvr, fwupgrade device can configured as options.
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static int cls_fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct switchbrd_priv *priv;
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struct platform_device **i2cbuses_pdev;
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struct platform_device *regio_pdev;
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struct platform_device *spiflash_pdev;
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//struct platform_device *xcvr_pdev;
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unsigned long rstart;
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int num_i2c_bus, i;
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int err;
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err = pci_enable_device(dev);
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if (err){
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dev_err(&dev->dev, "Failed to enable PCI device\n");
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goto err_exit;
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}
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/* Check for valid MMIO address */
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rstart = pci_resource_start(dev, MMIO_BAR);
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if (!rstart) {
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dev_err(&dev->dev, "Switchboard base address uninitialized, "
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"check FPGA\n");
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err = -ENODEV;
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goto err_disable_device;
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}
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dev_dbg(&dev->dev, "BAR%d res: 0x%lx-0x%llx\n", MMIO_BAR,
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rstart, pci_resource_end(dev, MMIO_BAR));
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priv = devm_kzalloc(&dev->dev,
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sizeof(struct switchbrd_priv), GFP_KERNEL);
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if (!priv){
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err = -ENOMEM;
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goto err_disable_device;
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}
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pci_set_drvdata(dev, priv);
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num_i2c_bus = ARRAY_SIZE(i2c_bus_configs);
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i2cbuses_pdev = devm_kzalloc(
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&dev->dev,
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num_i2c_bus * sizeof(struct platform_device*),
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GFP_KERNEL);
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reg_io_res[0].start += rstart;
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reg_io_res[0].end += rstart;
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spi_flash_res[0].start += rstart;
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spi_flash_res[0].end += rstart;
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regio_pdev = platform_device_register_resndata(
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&dev->dev, "cls-swbrd-io",
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-1,
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reg_io_res, ARRAY_SIZE(reg_io_res),
|
||
|
|
NULL, 0);
|
||
|
|
|
||
|
|
if (IS_ERR(regio_pdev)) {
|
||
|
|
dev_err(&dev->dev, "Failed to register cls-swbrd-io\n");
|
||
|
|
err = PTR_ERR(regio_pdev);
|
||
|
|
goto err_disable_device;
|
||
|
|
}
|
||
|
|
|
||
|
|
spiflash_pdev = platform_device_register_resndata(
|
||
|
|
&dev->dev, "cls-swbrd-fwug",
|
||
|
|
-1,
|
||
|
|
spi_flash_res, ARRAY_SIZE(spi_flash_res),
|
||
|
|
NULL, 0);
|
||
|
|
|
||
|
|
if (IS_ERR(spiflash_pdev)) {
|
||
|
|
dev_err(&dev->dev, "Failed to register firmware upgrade node\n");
|
||
|
|
err = PTR_ERR(spiflash_pdev);
|
||
|
|
goto err_unregister_regio;
|
||
|
|
}
|
||
|
|
|
||
|
|
for(i = 0; i < num_i2c_bus; i++){
|
||
|
|
|
||
|
|
i2c_bus_configs[i].res[0].start += rstart;
|
||
|
|
i2c_bus_configs[i].res[0].end += rstart;
|
||
|
|
|
||
|
|
dev_dbg(&dev->dev, "i2c-bus.%d: 0x%llx - 0x%llx\n",
|
||
|
|
i2c_bus_configs[i].id,
|
||
|
|
i2c_bus_configs[i].res[0].start,
|
||
|
|
i2c_bus_configs[i].res[0].end);
|
||
|
|
|
||
|
|
i2cbuses_pdev[i] = platform_device_register_resndata(
|
||
|
|
&dev->dev, "goodcores-i2c",
|
||
|
|
i2c_bus_configs[i].id,
|
||
|
|
i2c_bus_configs[i].res,
|
||
|
|
i2c_bus_configs[i].num_res,
|
||
|
|
&i2c_bus_configs[i].pdata,
|
||
|
|
sizeof(i2c_bus_configs[i].pdata));
|
||
|
|
|
||
|
|
if (IS_ERR(i2cbuses_pdev[i])) {
|
||
|
|
dev_err(&dev->dev, "Failed to register goodcores-i2c.%d\n",
|
||
|
|
i2c_bus_configs[i].id);
|
||
|
|
err = PTR_ERR(i2cbuses_pdev[i]);
|
||
|
|
goto err_unregister_ocore;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
priv->base = rstart;
|
||
|
|
priv->num_i2c_bus = num_i2c_bus;
|
||
|
|
priv->i2cbuses_pdev = i2cbuses_pdev;
|
||
|
|
priv->regio_pdev = regio_pdev;
|
||
|
|
priv->spiflash_pdev = spiflash_pdev;
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_unregister_ocore:
|
||
|
|
for(i = 0; i < num_i2c_bus; i++){
|
||
|
|
if(priv->i2cbuses_pdev[i]){
|
||
|
|
platform_device_unregister(priv->i2cbuses_pdev[i]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// err_unregister_spiflash:
|
||
|
|
// platform_device_unregister(spiflash_pdev);
|
||
|
|
err_unregister_regio:
|
||
|
|
platform_device_unregister(regio_pdev);
|
||
|
|
err_disable_device:
|
||
|
|
pci_disable_device(dev);
|
||
|
|
err_exit:
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void cls_fpga_remove(struct pci_dev *dev)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
struct switchbrd_priv *priv = pci_get_drvdata(dev);
|
||
|
|
|
||
|
|
for(i = 0; i < priv->num_i2c_bus; i++){
|
||
|
|
if(priv->i2cbuses_pdev[i])
|
||
|
|
platform_device_unregister(priv->i2cbuses_pdev[i]);
|
||
|
|
}
|
||
|
|
platform_device_unregister(priv->spiflash_pdev);
|
||
|
|
platform_device_unregister(priv->regio_pdev);
|
||
|
|
pci_disable_device(dev);
|
||
|
|
return;
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct pci_device_id pci_clsswbrd[] = {
|
||
|
|
{ PCI_VDEVICE(XILINX, FPGA_PCIE_DEVICE_ID) },
|
||
|
|
{0, }
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(pci, pci_clsswbrd);
|
||
|
|
|
||
|
|
static struct pci_driver clsswbrd_pci_driver = {
|
||
|
|
.name = DRV_NAME,
|
||
|
|
.id_table = pci_clsswbrd,
|
||
|
|
.probe = cls_fpga_probe,
|
||
|
|
.remove = cls_fpga_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_pci_driver(clsswbrd_pci_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Pradchaya P.<pphuchar@celestica.com>");
|
||
|
|
MODULE_DESCRIPTION("Celestica Silverstone switchboard driver");
|
||
|
|
MODULE_VERSION(MOD_VERSION);
|
||
|
|
MODULE_LICENSE("GPL");
|