2018-08-12 19:22:08 -05:00
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/**
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@file dal_kernel_io.h
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@author Copyright (C) 2012 Centec Networks Inc. All rights reserved.
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@date 2012-4-9
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@version v2.0
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*/
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#ifndef _DAL_KERNEL_H_
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#define _DAL_KERNEL_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(CONFIG_RESOURCES_64BIT) || defined(CONFIG_PHYS_ADDR_T_64BIT)
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#define PHYS_ADDR_IS_64BIT
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#endif
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#ifndef SDK_IN_USERMODE
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#ifdef PHYS_ADDR_IS_64BIT
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typedef long long intptr;
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typedef unsigned long long uintptr;
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#else
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typedef int intptr;
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typedef unsigned int uintptr;
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#endif
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#endif
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2020-08-06 05:16:11 -05:00
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#ifndef STATIC
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#define STATIC static
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#endif
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2018-08-12 19:22:08 -05:00
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#define DAL_PCI_READ_ADDR 0x0
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#define DAL_PCI_READ_DATA 0xc
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#define DAL_PCI_WRITE_ADDR 0x8
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#define DAL_PCI_WRITE_DATA 0x4
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#define DAL_PCI_STATUS 0x10
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#define DAL_PCI_STATUS_IN_PROCESS 31
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#define DAL_PCI_STATUS_BAD_PARITY 5
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#define DAL_PCI_STATUS_CPU_ACCESS_ERR 4
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#define DAL_PCI_STATUS_READ_CMD 3
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#define DAL_PCI_STATUS_REGISTER_ERR 1
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#define DAL_PCI_STATUS_REGISTER_ACK 0
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#define DAL_PCI_ACCESS_TIMEOUT 0x64
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#define DAL_NAME "linux_dal" /* "linux_dal" */
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#define DAL_DEV_MAJOR 198
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#define DAL_DEV_INTR_MAJOR_BASE 200
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#define DAL_DEV_NAME "/dev/" DAL_NAME
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#define DAL_ONE_KB 1024
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#define DAL_ONE_MB (1024*1024)
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2021-05-01 12:37:07 -05:00
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#define CTC_MAX_INTR_NUM 8
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2018-08-12 19:22:08 -05:00
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struct dal_chip_parm_s
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{
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2018-11-16 11:41:39 -06:00
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unsigned int lchip; /*tmp should be uint8*/
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2018-08-12 19:22:08 -05:00
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unsigned int fpga_id; /*tmp add*/
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unsigned int reg_addr;
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unsigned int value;
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};
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typedef struct dal_chip_parm_s dal_chip_parm_t;
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struct dal_intr_parm_s
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{
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unsigned int irq;
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unsigned int enable;
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};
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typedef struct dal_intr_parm_s dal_intr_parm_t;
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struct dal_irq_mapping_s
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{
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unsigned int hw_irq;
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unsigned int sw_irq;
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};
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typedef struct dal_irq_mapping_s dal_irq_mapping_t;
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struct dal_user_dev_s
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{
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unsigned int chip_num; /*output: local chip number*/
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2018-11-16 11:41:39 -06:00
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unsigned int lchip; /*input: local chip id*/
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2018-08-12 19:22:08 -05:00
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unsigned int phy_base0; /* low 32bits physical base address */
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unsigned int phy_base1; /* high 32bits physical base address */
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2021-05-01 12:37:07 -05:00
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unsigned int dma_phy_base0; /* low 32bits physical base address */
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unsigned int dma_phy_base1; /* high 32bits physical base address */
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2018-08-12 19:22:08 -05:00
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unsigned int bus_no;
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unsigned int dev_no;
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unsigned int fun_no;
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2020-08-06 05:16:11 -05:00
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unsigned int soc_active;
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void* virt_base[2]; /* !!!!warning!!!!Virtual base address; pointer void* must be last member */
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2018-08-12 19:22:08 -05:00
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};
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typedef struct dal_user_dev_s dal_user_dev_t;
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struct dal_pci_cfg_ioctl_s
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{
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2018-11-16 11:41:39 -06:00
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unsigned int lchip; /* Device ID */
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2018-08-12 19:22:08 -05:00
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unsigned int offset;
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unsigned int value;
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};
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typedef struct dal_pci_cfg_ioctl_s dal_pci_cfg_ioctl_t;
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2021-05-01 12:37:07 -05:00
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enum dal_msi_type_e
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{
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DAL_MSI_TYPE_MSI,
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DAL_MSI_TYPE_MSIX,
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DAL_MSI_TYPE_MAX
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};
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typedef enum dal_msi_type_e dal_msi_type_t;
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2018-08-12 19:22:08 -05:00
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struct dal_msi_info_s
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{
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unsigned int lchip;
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2021-05-01 12:37:07 -05:00
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unsigned int irq_base[CTC_MAX_INTR_NUM];
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2018-08-12 19:22:08 -05:00
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unsigned int irq_num;
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unsigned int msi_type;
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2018-08-12 19:22:08 -05:00
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};
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typedef struct dal_msi_info_s dal_msi_info_t;
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struct dal_intr_info_s
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{
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unsigned int irq;
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unsigned int irq_idx;
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};
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typedef struct dal_intr_info_s dal_intr_info_t;
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struct dal_dma_cache_info_s
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{
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unsigned long ptr;
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unsigned int length;
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};
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typedef struct dal_dma_cache_info_s dal_dma_cache_info_t;
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#define CMD_MAGIC 'C'
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#define CMD_WRITE_CHIP _IO(CMD_MAGIC, 0) /* for humber ioctrol*/
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#define CMD_READ_CHIP _IO(CMD_MAGIC, 1) /* for humber ioctrol*/
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#define CMD_GET_DEVICES _IO(CMD_MAGIC, 2)
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#define CMD_GET_DAL_VERSION _IO(CMD_MAGIC, 3)
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#define CMD_PCI_CONFIG_WRITE _IO(CMD_MAGIC, 4)
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#define CMD_PCI_CONFIG_READ _IO(CMD_MAGIC, 5)
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#define CMD_GET_DMA_INFO _IO(CMD_MAGIC, 6)
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#define CMD_REG_INTERRUPTS _IO(CMD_MAGIC, 7)
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#define CMD_UNREG_INTERRUPTS _IO(CMD_MAGIC, 8)
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#define CMD_EN_INTERRUPTS _IO(CMD_MAGIC, 9)
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#define CMD_I2C_READ _IO(CMD_MAGIC, 10)
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#define CMD_I2C_WRITE _IO(CMD_MAGIC, 11)
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#define CMD_GET_MSI_INFO _IO(CMD_MAGIC, 12)
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#define CMD_SET_MSI_CAP _IO(CMD_MAGIC, 13)
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#define CMD_IRQ_MAPPING _IO(CMD_MAGIC, 14)
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#define CMD_GET_INTR_INFO _IO(CMD_MAGIC, 15)
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#define CMD_CACHE_INVAL _IO(CMD_MAGIC, 16)
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#define CMD_CACHE_FLUSH _IO(CMD_MAGIC, 17)
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2020-08-06 05:16:11 -05:00
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#define CMD_GET_KNET_VERSION _IO(CMD_MAGIC, 18)
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#define CMD_CONNECT_INTERRUPTS _IO(CMD_MAGIC, 19)
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#define CMD_DISCONNECT_INTERRUPTS _IO(CMD_MAGIC, 20)
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#define CMD_SET_DMA_INFO _IO(CMD_MAGIC, 21)
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#define CMD_REG_DMA_CHAN _IO(CMD_MAGIC, 22)
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#define CMD_HANDLE_NETIF _IO(CMD_MAGIC, 23)
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2021-05-01 12:37:07 -05:00
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#define CMD_GET_WB_INFO _IO(CMD_MAGIC, 24)
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2018-08-12 19:22:08 -05:00
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enum dal_version_e
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{
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VERSION_MIN,
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VERSION_1DOT0,
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VERSION_1DOT1,
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VERSION_1DOT2,
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VERSION_1DOT3,
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VERSION_1DOT4,
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2018-08-12 19:22:08 -05:00
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VERSION_MAX
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};
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typedef enum dal_version_e dal_version_t;
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2020-08-06 05:16:11 -05:00
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struct dal_ops_s {
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int (*interrupt_connect)(unsigned int irq, int prio, void (*)(void*), void *data);
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int (*interrupt_disconnect)(unsigned int irq);
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};
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typedef struct dal_ops_s dal_ops_t;
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2018-08-12 19:22:08 -05:00
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/* We try to assemble a contiguous segment from chunks of this size */
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#define DMA_BLOCK_SIZE (512 * DAL_ONE_KB)
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2020-08-06 05:16:11 -05:00
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extern int dal_get_dal_ops(dal_ops_t **dal_ops);
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extern int dal_cache_inval(unsigned long ptr, unsigned int length);
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extern int dal_cache_flush(unsigned long ptr, unsigned int length);
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2021-05-01 12:37:07 -05:00
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extern int dal_dma_direct_read(unsigned char lchip, unsigned int offset, unsigned int* value);
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extern int dal_dma_direct_write(unsigned char lchip, unsigned int offset, unsigned int value);
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2018-08-12 19:22:08 -05:00
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#ifdef __cplusplus
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}
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#endif
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#endif
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