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sonic-buildimage/platform/centec-arm64/sai.mk

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[centec]: Add centec arm64 architecture support for E530 (#4641) summary of E530 platfrom: - CPU: CTC5236, arm64 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G. - device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports. - device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports. add new files in three directories: device/centec/arm64-centec_e530_24x2c-r0 device/centec/arm64-centec_e530_48t4x_p-r0 platform/centec-arm64 Co-authored-by: taocy <taocy2@centecnetworks.com> Co-authored-by: Gu Xianghong <gxh2001757@163.com> Co-authored-by: shil <shil@centecnetworks.com>
2020-08-06 05:16:11 -05:00
# Centec SAI
[centec]: reference to v1.11.0-1 sai debian package for master (#13206)
2023-01-03 11:53:46 -06:00
export CENTEC_SAI_VERSION = 1.11.0-1
[centec]: Add centec arm64 architecture support for E530 (#4641) summary of E530 platfrom: - CPU: CTC5236, arm64 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G. - device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports. - device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports. add new files in three directories: device/centec/arm64-centec_e530_24x2c-r0 device/centec/arm64-centec_e530_48t4x_p-r0 platform/centec-arm64 Co-authored-by: taocy <taocy2@centecnetworks.com> Co-authored-by: Gu Xianghong <gxh2001757@163.com> Co-authored-by: shil <shil@centecnetworks.com>
2020-08-06 05:16:11 -05:00
export CENTEC_SAI = libsai_$(CENTEC_SAI_VERSION)_$(PLATFORM_ARCH).deb
[centec]: fix docker syncd rpc compile(#11097) Change makefile to reference to new SAI dev for docker-syncd-centec-rpc compile Co-authored-by: yoush <yoush@centec.com>
2022-06-16 17:27:57 -05:00
export CENTEC_SAI_DEV = libsai-dev_$(CENTEC_SAI_VERSION)_$(PLATFORM_ARCH).deb
[Centec] Upgrade Centec platform containers(syncd/saiserver/syncd-rpc) to bullseye (#13375) Why I did it Upgrade both Centec X86 and ARM64 platform containers(syncd/saiserver/syncd-rpc) to bullseye Optimize Centec X86 platform makefile, change sdk.mk to sai.mk How I did it Modify Makefile and Dockerfile to use bullseye Change filename form sdk.mk to sai.mk, optimize and modify related files How to verify it For Centec X86 platform, compile the code with : a) make configure PLATFORM=centec; b) make all For Centec ARM64 platform, cmpile the code with: a) make configure PLATFORM=centec-arm64 PLATFORM_ARCH=arm64; b) make all Verifiy the sonic-centec.bin and sonic-centec-arm64.bin on Centec chip based board.
2023-02-06 11:26:35 -06:00
export CENTEC_SAI_URL_PREFIX = "https://github.com/CentecNetworks/sonic-binaries/raw/master/$(PLATFORM_ARCH)/sai"
[centec]: Add centec arm64 architecture support for E530 (#4641) summary of E530 platfrom: - CPU: CTC5236, arm64 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G. - device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports. - device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports. add new files in three directories: device/centec/arm64-centec_e530_24x2c-r0 device/centec/arm64-centec_e530_48t4x_p-r0 platform/centec-arm64 Co-authored-by: taocy <taocy2@centecnetworks.com> Co-authored-by: Gu Xianghong <gxh2001757@163.com> Co-authored-by: shil <shil@centecnetworks.com>
2020-08-06 05:16:11 -05:00
[Centec] Upgrade Centec platform containers(syncd/saiserver/syncd-rpc) to bullseye (#13375) Why I did it Upgrade both Centec X86 and ARM64 platform containers(syncd/saiserver/syncd-rpc) to bullseye Optimize Centec X86 platform makefile, change sdk.mk to sai.mk How I did it Modify Makefile and Dockerfile to use bullseye Change filename form sdk.mk to sai.mk, optimize and modify related files How to verify it For Centec X86 platform, compile the code with : a) make configure PLATFORM=centec; b) make all For Centec ARM64 platform, cmpile the code with: a) make configure PLATFORM=centec-arm64 PLATFORM_ARCH=arm64; b) make all Verifiy the sonic-centec.bin and sonic-centec-arm64.bin on Centec chip based board.
2023-02-06 11:26:35 -06:00
$(CENTEC_SAI)_URL = $(CENTEC_SAI_URL_PREFIX)/$(CENTEC_SAI)
$(CENTEC_SAI_DEV)_URL = $(CENTEC_SAI_URL_PREFIX)/$(CENTEC_SAI_DEV)
[centec]: fix docker syncd rpc compile(#11097) Change makefile to reference to new SAI dev for docker-syncd-centec-rpc compile Co-authored-by: yoush <yoush@centec.com>
2022-06-16 17:27:57 -05:00
$(eval $(call add_conflict_package,$(CENTEC_SAI_DEV),$(LIBSAIVS_DEV)))
[centec]: Add centec arm64 architecture support for E530 (#4641) summary of E530 platfrom: - CPU: CTC5236, arm64 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G. - device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports. - device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports. add new files in three directories: device/centec/arm64-centec_e530_24x2c-r0 device/centec/arm64-centec_e530_48t4x_p-r0 platform/centec-arm64 Co-authored-by: taocy <taocy2@centecnetworks.com> Co-authored-by: Gu Xianghong <gxh2001757@163.com> Co-authored-by: shil <shil@centecnetworks.com>
2020-08-06 05:16:11 -05:00
SONIC_ONLINE_DEBS += $(CENTEC_SAI)
[centec]: fix docker syncd rpc compile(#11097) Change makefile to reference to new SAI dev for docker-syncd-centec-rpc compile Co-authored-by: yoush <yoush@centec.com>
2022-06-16 17:27:57 -05:00
SONIC_ONLINE_DEBS += $(CENTEC_SAI_DEV)
[Centec] Upgrade Centec platform containers(syncd/saiserver/syncd-rpc) to bullseye (#13375) Why I did it Upgrade both Centec X86 and ARM64 platform containers(syncd/saiserver/syncd-rpc) to bullseye Optimize Centec X86 platform makefile, change sdk.mk to sai.mk How I did it Modify Makefile and Dockerfile to use bullseye Change filename form sdk.mk to sai.mk, optimize and modify related files How to verify it For Centec X86 platform, compile the code with : a) make configure PLATFORM=centec; b) make all For Centec ARM64 platform, cmpile the code with: a) make configure PLATFORM=centec-arm64 PLATFORM_ARCH=arm64; b) make all Verifiy the sonic-centec.bin and sonic-centec-arm64.bin on Centec chip based board.
2023-02-06 11:26:35 -06:00
$(CENTEC_SAI_DEV)_DEPENDS += $(CENTEC_SAI)
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